MC908GR16AVFAER Freescale Semiconductor, MC908GR16AVFAER Datasheet - Page 66
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MC908GR16AVFAER
Manufacturer Part Number
MC908GR16AVFAER
Description
IC MCU 8BIT 16K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GR16ACFAE.pdf
(270 pages)
Specifications of MC908GR16AVFAER
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
LIN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
37
Number Of Timers
4
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR16AVFAER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Clock Generator Module (CGM)
depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at start up.
4.4.9 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks.
CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software
programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK,
divided by two.
4.4.10 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
4.5 CGM Registers
These registers control and monitor operation of the CGM:
Figure 4-3
66
NOTES:
Addr.
$003A
$003B
$0036
$0037
$0038
$0039
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
•
•
•
•
•
PLL control register (PCTL) — See
PLL bandwidth control register (PBWC) — see
PLL multiplier select register high (PMSH) — see
PLL multiplier select register low (PMSL) — see
PLL VCO range select register (PMRS) — see
PLL Multiplier Select High
PLL Multiplier Select Low
PLL VCO Select Range
is a summary of the CGM registers.
PLL Bandwidth Control
Register Name
PLL Control Register
Reserved Register
Register (PBWC)
Register (PMSH)
Register (PMRS)
Register (PMSL)
See page 67.
See page 68.
See page 69.
See page 70.
See page 70.
(PCTL)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Figure 4-3. CGM I/O Register Summary
MC68HC908GR16A Data Sheet, Rev. 1.0
PLLIE
AUTO
MUL7
VRS7
Bit 7
0
0
0
0
0
0
0
0
= Unimplemented
4.5.1 PLL Control Register
LOCK
MUL6
VRS6
PLLF
6
0
0
0
0
1
1
0
0
PLLON
MUL5
VRS5
ACQ
4.5.5 PLL VCO Range Select Register
4.5.2 PLL Bandwidth Control Register
5
1
0
0
0
0
0
0
0
4.5.4 PLL Multiplier Select Register Low
4.5.3 PLL Multiplier Select Register High
MUL4
VRS4
BCS
R
4
0
0
0
0
0
0
0
0
0
= Reserved
MUL11
MUL3
VRS3
R
R
3
0
0
0
0
0
0
0
MUL10
MUL2
VRS2
R
R
2
0
0
0
0
0
0
0
Freescale Semiconductor
VPR1
MUL9
MUL1
VRS1
R
1
0
0
0
0
0
0
0
VPR0
MUL8
MUL0
VRS0
Bit 0
R
R
0
0
0
0
0
1
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