MC908AP32CFAER Freescale Semiconductor, MC908AP32CFAER Datasheet - Page 101

• Manufacturer Part Number: MC908AP32CFAER
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AP32CFAER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 ICLK cycles to allow resetting of external
peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (see
Figure
POR (see
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
7.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 + 32 ICLK cycles. Thirty-two ICLK cycles later, the CPU and memories are released from reset to
allow the reset vector sequence to occur.
Freescale Semiconductor
7-5). An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or
Figure
ICLK
RST
IAB
For LVI or POR resets, the SIM cycles through 4096 + 32 ICLK cycles
during which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST shown in
Figure
IRST
ICLK
RST
IAB
7-6).
PC
7-5.
ILLEGAL ADDRESS RST
RST PULLED LOW BY MCU
ILLEGAL OPCODE RST
Figure 7-6. Sources of Internal Reset
MC68HC908AP Family Data Sheet, Rev. 4
Figure 7-4. External Reset Timing
Figure 7-5. Internal Reset Timing
32 CYCLES
COPRST
POR
LVI
NOTE
INTERNAL RESET
32 CYCLES
VECT H VECT L
VECTOR HIGH
Reset and System Initialization
101