S9S08DZ128F2VLL Freescale Semiconductor, S9S08DZ128F2VLL Datasheet - Page 176
S9S08DZ128F2VLL
Manufacturer Part Number
S9S08DZ128F2VLL
Description
MCU 128K FLASH AUTO 100-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08DV96CLF.pdf
(458 pages)
Specifications of S9S08DZ128F2VLL
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Processor Series
S08D
Core
HCS08
Data Bus Width
8 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S08DZ128F2VLL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)
176
DIV32
Field
VDIV
3:0
4
Divide-by-32 Enable — Controls an additional divide-by-32 factor to the external reference clock for the FLL
when RANGE bit is set. When the RANGE bit is 0, this bit has no effect. Writes to this bit are ignored if PLLS bit
is set.
0 Divide-by-32 is disabled.
1 Divide-by-32 is enabled when RANGE=1.
VCO Divider — Selects the amount to divide down the VCO output of PLL. The VDIV bits establish the
multiplication factor (M) applied to the reference clock frequency.
0000 Encoding 0 — Reserved.
0001 Encoding 1 — Multiply by 4.
0010 Encoding 2 — Multiply by 8.
0011 Encoding 3 — Multiply by 12.
0100 Encoding 4 — Multiply by 16.
0101 Encoding 5 — Multiply by 20.
0110 Encoding 6 — Multiply by 24.
0111 Encoding 7 — Multiply by 28.
1000 Encoding 8 — Multiply by 32.
1001 Encoding 9 — Multiply by 36.
1010 Encoding 10 — Multiply by 40.
1011 Encoding 11 — Reserved (default to M=40).
11xx Encoding 12-15 — Reserved (default to M=40).
Table 8-7. MCG Control Register 3 Field Descriptions (continued)
MC9S08DZ128 Series Data Sheet, Rev. 1
Description
Freescale Semiconductor
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