S9S08DZ128F2VLL Freescale Semiconductor, S9S08DZ128F2VLL Datasheet - Page 280
S9S08DZ128F2VLL
Manufacturer Part Number
S9S08DZ128F2VLL
Description
MCU 128K FLASH AUTO 100-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08DV96CLF.pdf
(458 pages)
Specifications of S9S08DZ128F2VLL
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Processor Series
S08D
Core
HCS08
Data Bus Width
8 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S08DZ128F2VLL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
12.4.2
1
280
IDE is 0.
ID[10:3]
ID[6:0]
Field
Field
RTR
7:1
7:0
0
Reset:
Reset:
Reset:
W
W
W
R
R
R
IDR0–IDR3 for Standard Identifier Mapping
Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the
most significant bit and is transmitted first on the CAN bus during the arbithation procedure. The priority of an
identifier is defined to be highest for the smallest binary number.
Remote Transmission Request — This flag reflects the status of the remote transmission request bit in the
CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the
transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of
the RTR bit to be sent.
0 Data frame
1 Remote frame
Standard Format Identifier — The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the
most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an
identifier is defined to be highest for the smallest binary number. See also ID bits in
ID10
ID6
ID2
7
x
Figure 12-28. Identifier Register 3 (IDR3) — Extended Identifier Mapping
7
x
7
x
Table 12-28. IDR3 Register Field Descriptions — Extended
Table 12-29. IDR0 Register Field Descriptions — Standard
Figure 12-29. Identifier Register 0 — Standard Mapping
Figure 12-30. Identifier Register 1 — Standard Mapping
= Unused; always read ‘x’
ID5
ID9
ID1
6
x
6
x
6
x
MC9S08DZ128 Series Data Sheet, Rev. 1
ID4
ID8
ID0
5
x
5
x
5
x
RTR
ID3
ID7
4
x
4
x
4
x
Description
Description
IDE
ID2
ID6
x
x
x
3
3
3
(1)
ID1
ID5
2
x
2
x
2
x
Table
Freescale Semiconductor
ID0
ID4
12-30.
x
x
x
1
1
1
RTR
ID3
0
x
0
x
0
x
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