C8051F504-IQ Silicon Laboratories Inc, C8051F504-IQ Datasheet - Page 126

• Manufacturer Part Number: C8051F504-IQ
• Description: IC 8051 MCU 32K FLASH 48-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F50xr

Specifications of C8051F504-IQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-QFP
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 40
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 32x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 32-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1527 - KIT DEV FOR C8051F50X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1518

C8051F50x/F51x
SFR Definition 14.6. EIP2: Extended Interrupt Priority Enabled 2
SFR Address = 0xF7; SFR Page = 0x00 and 0x0F
14.3. External Interrupts INT0 and INT1
The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi-
tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “26.1. Timer 0 and Timer 1” on page 267) select level or
edge sensitive. The table below lists the possible configurations.
INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 14.7). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register XBR0 (see Section “20.3. Priority Crossbar
Decoder” on page 180 for complete details on configuring the Crossbar).
126
IT0
1
1
0
0
Name
Reset
7:3
Bit
Type
2
1
0
Bit
Unused
PCAN0
PREG0
Name
PMAT
IN0PL
0
1
0
1
R
7
0
Read = 00000b; Write = Don’t Care.
Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
CAN0 Interrupt Priority Control.
This bit sets the priority of the CAN0 interrupt.
0: CAN0 interrupt set to low priority level.
1: CAN0 interrupt set to high priority level.
Voltage Regulator Dropout Interrupt Priority Control.
This bit sets the priority of the Voltage Regulator Dropout interrupt.
0: Voltage Regulator Dropout interrupt set to low priority level.
1: Voltage Regulator Dropout interrupt set to high priority level.
INT0 Interrupt
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
R
6
0
R
5
0
Rev. 1.2
R
4
0
Function
IT1
1
1
0
0
R
3
0
IN1PL
0
1
0
1
PMAT
R/W
2
0
INT1 Interrupt
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
PCAN0
R/W
1
0
PREG0
R/W
0
0