R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 445

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 416 of 573
25.4.5
In slave receive mode, the master device outputs the transmit clock and data, and the slave device returns an
acknowledge signal.
Figures 25.11 and 25.12 show the Operating Timing in Slave Receive Mode (I
The receive procedure and operation in slave receive mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled), and set bits WAIT and MLS in the
(2) When the slave address matches at the first frame after detecting the start condition, the slave device
(3) Read the ICDRR register every time the RDRF bit is set to 1. If the 8th clock cycle falls while the RDRF bit
(4) Reading the last byte is also performed by reading the ICDRR register.
ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). Then, set bits TRS and MST
in the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.
outputs the level set in the ACKBT bit in the ICIER register to the SDA pin at the rising edge of the 9th
clock cycle. Since the RDRF bit in the ICSR register is set to 1 simultaneously, dummy read the ICDRR
register (the read data is unnecessary because it indicates the slave address and R/W).
is set to 1, the SCL signal is fixed “L” until the ICDRR register is read. The setting change of the
acknowledge signal returned to the master device before reading the ICDRR register takes affect from the
following transfer frame.
Slave Receive Operation
2
C bus Interface Mode).
25. I
2
C bus Interface