MC908AP32ACFAE Freescale Semiconductor, MC908AP32ACFAE Datasheet - Page 236

• Manufacturer Part Number: MC908AP32ACFAE
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AP32ACFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: HC08AP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908AP64E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Multi-Master IIC Interface (MMIIC)
MMSRW — MMIIC Slave Read/Write Select
MMRXAK — MMIIC Receive Acknowledge
MMCRCBF — CRC Data Buffer Full Flag
MMTXBE — MMIIC Transmit Buffer Empty
MMRXBF — MMIIC Receive Buffer Full
14.6.5
236
This bit indicates the data direction when the module is in slave mode. It is updated after the calling
address is received from a master device. MMSRW = 1 when the calling master is reading data from
the module (slave transmit mode). MMSRW = 0 when the master is writing data to the module (receive
mode).
When this bit is cleared, it indicates an acknowledge signal has been received after the completion of
eight data bits transmission on the bus. When MMRXAK is set, it indicates no acknowledge signal has
been detected at the 9th clock; the module will release the SDA line for the master to generate STOP
or repeated START condition. Reset sets this bit.
This flag is set when the CRC data register (MMCRCDR) is loaded with a CRC byte for the current
received or transmitted data.
In transmit mode, after a byte of data has been sent (MMTXIF = 1), the MMCRCBF will be set when
the CRC byte has been generated and ready in the MMCRCDR. The content of the MMCRCDR should
be copied to the MMDTR for transmission.
In receive mode, the MMCRCBF is set when the CRC byte has been generated and ready in
MMCRCDR, for the current byte of received data.
The MMCRCBF bit is cleared when the CRC data register is read. Reset also clears this bit.
This flag indicates the status of the data transmit register (MMDTR). When the CPU writes the data to
the MMDTR, the MMTXBE flag will be cleared. MMTXBE is set when MMDTR is emptied by a transfer
of its data to the output circuit. Reset sets this bit.
This flag indicates the status of the data receive register (MMDRR). When the CPU reads the data
from the MMDRR, the MMRXBF flag will be cleared. MMRXBF is set when MMDRR is full by a transfer
of data from the input circuit to the MMDRR. Reset clears this bit.
1 = Slave mode transmit
0 = Slave mode receive
1 = No acknowledge signal received at 9th clock
0 = Acknowledge signal received at 9th clock
1 = Data ready in CRC data register (MMCRCDR)
0 = Data not ready in CRC data register (MMCRCDR)
1 = Data transmit register empty
0 = Data transmit register full
1 = Data receive register full
0 = Data receive register empty
MMIIC
Address:
Reset:
Read:
Write:
Data Transmit Register (MMDTR)
MMTD7
$004C
Bit 7
Figure 14-8. MMIIC Data Transmit Register (MMDTR)
0
MMTD6
MC68HC908AP A-Family Data Sheet, Rev. 3
6
0
MMTD5
5
0
MMTD4
4
0
MMTD3
3
0
MMTD2
2
0
MMTD1
1
0
Freescale Semiconductor
MMTD0
Bit 0
0