MC9S12XET256CAG Freescale Semiconductor, MC9S12XET256CAG Datasheet - Page 180

• Manufacturer Part Number: MC9S12XET256CAG
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XET256CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XE
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.104 Port F Reduced Drive Register (RDRF)
2.3.105 Port F Pull Device Enable Register (PERF)
180
Address 0x037B
Address 0x037C
Write: Anytime.
Write: Anytime.
RDRF
PERF
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
Port F reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced independent of the
function used on the pins. If a pin is used as input this bit has no effect.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
Port F pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset all pull devices are enabled.
1 Pull device enabled.
0 Pull device disabled.
RDRF7
PERF7
0
1
7
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTF or PTIF registers, when changing the
DDRF register.
RDRF6
PERF6
Figure 2-103. Port F Pull Device Enable Register (PERF)
0
1
6
6
Figure 2-102. Port F Reduced Drive Register (RDRF)
Table 2-100. PERF Register Field Descriptions
Table 2-99. RDRF Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
RDRF5
PERF5
0
1
5
5
RDRF4
PERF4
NOTE
0
1
4
4
Description
Description
RDRF3
PERF3
3
0
3
1
RDRF2
PERF2
0
1
2
2
Access: User read/write
Access: User read/write
Freescale Semiconductor
RDRF1
PERF1
0
1
1
1
RDRF0
PERF0
0
1
0
0
(1)
(1)