M38588GCSP#U0 Renesas Electronics America, M38588GCSP#U0 Datasheet - Page 16

• Manufacturer Part Number: M38588GCSP#U0
• Description: IC 740/3858 MCU QZ-ROM 42DIP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38588GCSP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 12.5MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: QzROM
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 9x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3858 Group
Fig. 11 Port block diagram (2)
REJ03B0139-0111
page 14 of 73
( 1 1 ) P o r t P 2
( 1 5 ) P o r t s P 4
(9) Port P2
( 1 3 ) P o r t s P 0
D a t a b u s
S e r i a l I / O 1 s y n c h r o n o u s
S e r i a l I / O 1 m o d e s e l e c t i o n b i t
D a t a b u s
Data bus
Serial I/O1 enable bit
Data bus
c l o c k s e l e c t i o n b i t
S e r i a l I / O 1 e n a b l e b i t
R e c e i v e e n a b l e b i t
S e r i a l I / O 1 e n a b l e b i t
4
Rev.1.11
S e r i a l I / O 1 c l o c k o u t p u t
6
A / D c o n v e r t e r i n p u t
1
4
, P 4
- P 0
P u l l - u p c o n t r o l b i t
P o r t l a t c h
D i r e c t i o n
r e g i s t e r
2
7
D i r e c t i o n
r e g i s t e r
Port latch
, P 3
P u l l - u p c o n t r o l b i t
Port latch
D i r e c t i o n
r e g i s t e r
P o r t l a t c h
D i r e c t i o n
r e g i s t e r
P u l l - u p c o n t r o l b i t
0
- P 3
Dec 18, 2008
P u l l - u p c o n t r o l b i t
4
A n a l o g i n p u t p i n s e l e c t i o n b i t
A n a l o g i n p u t p o r t s e l e c t i o n s w i t c h b i t
I n t e r r u p t i n p u t
S e r i a l I / O 1 i n p u t
E x t e r n a l c l o c k i n p u t
( 1 0 ) P o r t P 2
(16) Port P4
(12) Port P2
Data bus
(14) Port P4
S e r i a l I / O 1 e n a b l e b i t
Serial I/O1 mode selection bit
P - c h a n n e l o u t p u t d i s a b l e b i t
Data bus
Transmit enable bit
comparison signal control bit
Data bus
S
c o m p a r i s o n s i g n a l o u t p u t
Data bus
R D Y 1
Serial I/O1 enable bit
5
P u l s e o u t p u t m o d e
3
7
o u t p u t e n a b l e b i t
S e r i a l r e a d y o u t p u t
0
Serial I/O1 output
Direction
register
P o r t l a t c h
Serial I/O2 I/O
S e r i a l I / O 2 I / O
P u l s e o u t p u t m o d e
T i m e r o u t p u t
Timer output
Direction
register
P o r t l a t c h
Pulse output mode
Port latch
Direction
register
P u l l - u p c o n t r o l b i t
Port latch
D i r e c t i o n
r e g i s t e r
P u l l - u p c o n t r o l b i t
P u l l - u p c o n t r o l b i t
P u l l - u p c o n t r o l b i t
Interrupt input
C N T R
CNTR
1
i n t e r r u p t
i n p u t
0
interrupt
input