MCF5329CVM240J Freescale Semiconductor, MCF5329CVM240J Datasheet - Page 20

• Manufacturer Part Number: MCF5329CVM240J
• Description: IC MPU RISC 240MHZ 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF532xr

Specifications of MCF5329CVM240J

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, LCD, PWM, WDT
• Number Of I /o: 94
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Family Name: MPC5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 240MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.6/1.95/2.75/3.6V
• Operating Supply Voltage (min): 1.4/1.7/2.25/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Processor Series: MCF532xx
• Core: ColdFire V3
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Electrical Characteristics
5.6
Table 9
20
1
2
3
4
5
6
7
8
9
10
11
Num
The maximum allowable input clock frequency when booting with the PLL enabled is 24MHz. For higher input clock
frequencies the processor must boot in LIMP mode to avoid violating the maximum allowable CPU frequency.
All internal registers retain data at 0 Hz.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
Proper PC board layout procedures must be followed to achieve specifications.
This parameter is guaranteed by design rather than 100% tested.
This specification is the PLL lock time only and does not include oscillator start-up time.
C
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the PLL circuitry via PLL V
the Cjitter percentage for a given interval.
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod.
Modulation percentage applies over an interval of 10 μs, or equivalently the modulation rate is 100 KHz.
12
13
14
17
18
19
Modulation range determined by hardware design.
PCB_EXTAL
lists processor bus input timings.
External Interface Timing Characteristics
Crystal capacitive load
Discrete load capacitance for XTAL
Discrete load capacitance for EXTAL
CLKOUT Period Jitter,
Frequency Modulation Range Limit
(f
VCO Frequency. f
sys
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter
Max must not be exceeded)
and C
All processor bus timings are synchronous; that is, input setup/hold and output delay with
respect to the rising edge of a reference clock. The reference clock is the FB_CLK output.
All other timing relationships can be derived from these values. Timings listed in
are shown in
PCB_XTAL
vco
Figure 7
Table 8. PLL Electrical Characteristics (continued)
= (f
Characteristic
are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
MCF532x ColdFire
3, 4, 7, 8, 9
ref *
and
PFD)/4
Measured at f
Figure
3, 10, 11
DD
8.
, EV
®
Microprocessor Data Sheet, Rev. 5
DD
SYS
NOTE
, and V
Max
SS
and variation in crystal oscillator frequency increase
C
Symbol
C
L_EXTAL
C
C
L_XTAL
f
C
vco
jitter
mod
L
Value
Min.
350
0.8
—
—
C
C
See crystal
C
Table 9
C
PCB_EXTAL
Freescale Semiconductor
PCB_XTAL
S_EXTAL
2*C
S_XTAL
2*C
Value
Max.
spec
TBD
540
2.2
10
L
L
–-
–
–
–
7
7
% f
% f
%f
MHz
Unit
pF
pF
sys/3
sys/3
sys/3
sys
.