MC68HC711D3CFNE3 Freescale Semiconductor, MC68HC711D3CFNE3 Datasheet - Page 35

IC MCU 8BIT 2MHZ 44-PLCC

MC68HC711D3CFNE3

Manufacturer Part Number
MC68HC711D3CFNE3
Description
IC MCU 8BIT 2MHZ 44-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711D3CFNE3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
26
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

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Freescale Semiconductor
DIRECT
INDXD,X
INDXD,Y
RTS, RETURN FROM SUBROUTINE
JSR, JUMP TO SUBROUTINE
EXTEND
BSR, BRANCH TO SUBROUTINE
SWI, SOFTWARE INTERRUPT
RTN
RTN
RTN
RTN
RTN
RTN
RTN
WAI, WAIT FOR INTERRUPT
PC
PC
PC
PC
PC
PC
PC
PC
NEXT MAIN INSTR
NEXT MAIN INSTR
NEXT MAIN INSTR
NEXT MAIN INSTR
NEXT MAIN INSTR
MAIN PROGRAM
MAIN PROGRAM
MAIN PROGRAM
MAIN PROGRAM
MAIN PROGRAM
MAIN PROGRAM
MAIN PROGRAM
SUBROUTINE
$AD = JSR
$AD = JSR
$BD = JSR
$8D = BSR
$9D = JSR
$18 = PRE
$39 = RTS
$3F = SWI
$3E = WAI
dd
hh
rr
ff
ff
ll
Figure 3-2. Stacking Operations
SP+2
SP+1
SP-9
SP-8
SP-7
SP-6
SP-5
SP-4
SP-3
SP-2
SP-2
SP-2
SP-1
SP-1
SP-1
MC68HC711D3 Data Sheet, Rev. 2.1
SP
SP
SP
SP
INDEX REGISTER (X
INDEX REGISTER (Y
INDEX REGISTER (X
INDEX REGISTER (Y
CONDITION CODE
ACMLTR B
ACMLTR A
STACK
STACK
STACK
STACK
RTN
RTN
RTN
RTN
RTN
RTN
RTN
RTN
H
H
H
H
L
L
L
L
H
H
L
L
)
)
)
)
RTI, RETURN FROM INTERRUPT
JMP, JUMP
INDXD,X
INDXD,Y
EXTND
LEGEND:
PC
RTN
RTN
RTN
INTERRUPT PROGRAM
dd
hh
rr
H
ff
L
ll
Address of next instruction in main program to be
executed upon return from subroutine
Most significant byte of return address
Least significant byte of return address
Shaded cells show stack pointer position after
operation is complete.
8-bit direct address ($0000–$00FF) (high byte
assumed to be $00).
8-bit positive offset $00 (0) to $FF (256) is added
to index.
High-order byte of 16-bit extended address.
Low-order byte of 16-bit extended address.
Signed-relative offset $80 (–128) to $7F (+127)
(offset relative to the address following the
machine code offset byte).
$3B = RTI
X + ff
X + ff
hh ll
PC
PC
PC
NEXT INSTRUCTION
NEXT INSTRUCTION
NEXT INSTRUCTION
MAIN PROGRAM
MAIN PROGRAM
MAIN PROGRAM
$6E = JMP
$18 = PRE
$6E = JMP
$7E = JMP
hh
ff
ff
ll
SP+1
SP+2
SP+3
SP+4
SP+5
SP+6
SP+7
SP+8
SP+9
SP
INDEX REGISTER (X
INDEX REGISTER (Y
INDEX REGISTER (X
INDEX REGISTER (Y
CONDITION CODE
ACMLTR B
ACMLTR A
STACK
RTN
RTN
CPU Registers
H
L
H
H
L
L
)
)
)
)
35

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