DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 598
DF2117VT20V
Manufacturer Part Number
DF2117VT20V
Description
MCU 16BIT FLASH 3V 160K 144-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2117VT20HV.pdf
(1040 pages)
Specifications of DF2117VT20V
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 18 I
18.3.8
ICXR enables or disables the I
indicates the status of receive/transmit operations.
Rev. 2.00 Sep. 28, 2009 Page 556 of 994
REJ09B0452-0200
Bit
7
6
Bit Name
STOPIM
HNDS
I
2
C Bus Extended Control Register (ICXR)
2
C Bus Interface (IIC)
Initial
Value
0
0
2
C bus interface interrupt generation and handshake control, and
R/W
R/W
R/W
Description
Stop Condition Interrupt Source Mask
Enables or disables the interrupt generation when the
stop condition is detected in slave mode.
0: Enables IRIC flag setting and interrupt generation
1: Disables IRIC flag setting and interrupt generation
for the selection of reception with handshaking.
0: Disables handshake control
1: Enables handshake control
Note: When the IIC module is in use, be sure to set this
When the HNDS bit is cleared to 0 and a round of
reception is completed with ICDRR empty (the ICDRF
flag is 0), successive reception will proceed with the
next round of reception. At the same time, a clock is
continuously supplied over the SCL line.
In this case, the sequence of operations should be
such that unnecessary clock cycles are not output to
the bus after reception of the last of the data.
When the HNDS bit is set to 1, SCL is fixed low and
clock output stops on completion of reception. SCL is
released and reception of the next frame is enabled by
reading the receive data from ICDR.
Enables or disables handshake control in receive mode
when the stop condition is detected (STOP = 1 or
ESTP = 1) in slave mode.
when the stop condition is detected.
bit to 1.
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