HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 98

• Manufacturer Part Number: HD64F2218UTF24
• Description: IC H8S MCU FLASH 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2218UTF24

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: SCI, SmartCard, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2.4.4
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Rev.7.00 Dec. 24, 2008 Page 42 of 698
REJ09B0074-0700
Bit
7
6
5
4
3
2
Bit Name
I
UI
H
U
N
Z
Condition-Code Register (CCR)
Initial Value
1
undefined
undefined
undefined
undefined
undefined
R/W Description
R/W Interrupt Mask Bit
R/W User Bit or Interrupt Mask Bit
R/W Half-Carry Flag
R/W User Bit
R/W Negative Flag
R/W Zero Flag
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set to 1
by hardware at the start of an exception-handling
sequence. For details, refer to section 5, Interrupt
Controller.
Can be written and read by software using the LDC, STC,
ANDC, ORC, and XORC instructions. This bit cannot be
used as an interrupt mask bit in this LSI.
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B or
NEG.B instruction is executed, this flag is set to 1 if there is
a carry or borrow at bit 3, and cleared to 0 otherwise. When
the ADD.W, SUB.W, CMP.W, or NEG.W instruction is
executed, the H flag is set to 1 if there is a carry or borrow
at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag
is set to 1 if there is a carry or borrow at bit 27, and cleared
to 0 otherwise.
Can be written and read by software using the LDC, STC,
ANDC, ORC, and XORC instructions.
Stores the value of the most significant bit of data as a sign
bit.
Set to 1 to indicate zero data, and cleared to 0 to indicate
non-zero data.