HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 51
![IC H8S MCU FLASH 128K 100-TQFP](/photos/12/40/124067/hd64f2218utf24_sml.jpg)
HD64F2218UTF24
Manufacturer Part Number
HD64F2218UTF24
Description
IC H8S MCU FLASH 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Specifications of HD64F2218UTF24
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2218UTF24V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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6. Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16),
or 32-bit (#xx:32) immediate data as an operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
7. Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and
BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and
added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch
address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the
displacement is added is the address of the first byte of the next instruction, so the possible
branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to
+16384 words) from the branch instruction. The resulting value should be an even number.
8. Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
second byte of the instruction specifies a memory operand by an 8-bit absolute address. This
memory operand contains a branch address. The upper bits of the absolute address are all assumed
to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'00000000 to
H'000000FF in advanced mode). In normal mode the memory operand is a word operand and the
branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the
first byte of which is assumed to be all 0 (H'00).
Note that the first part of the address range is also the exception vector area. For further details
refer to the relevant microcontroller hardware manual.
Specified
by @aa:8
Figure 1.13 Branch Address Specification in Memory Indirect Mode
(a) Normal Mode
Branch address
Specified
by @aa:8
Rev. 4.00 Feb 24, 2006 page 35 of 322
(b) Advanced Mode
Branch address
Reserved
REJ09B0139-0400
Section 1 CPU
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