M308A5SGP#U5 Renesas Electronics America, M308A5SGP#U5 Datasheet - Page 4

• Manufacturer Part Number: M308A5SGP#U5
• Description: MCU ROMLESS 12K RAM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M308A5SGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 81
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 18x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M32C/8A Group
REJ03B0213-0111 Rev.1.11 Mar 31, 2009
Page 2 of 66
Table 1.1
CPU
Memory
Power Supply Voltage Detection
External
Bus
Expansion
Clock
Interrupts
Watchdog Timer
DMA
Timer
Item
Central processing unit
ROM, RAM
Bus / memory expansion
function
Clock generation circuits • 4 circuits:
DMAC
DMACII
Timer A
Timer B
Timer function for
3-phase motor control
Specifications (144-Pin Package) (1/2)
Function
M32C/80 core (multiplier: 16 bits × 16 bits → 32 bits,
• Basic instructions: 108
• Minimum instruction execution time:
• Operating mode: microprocessor mode
See Table 1.5 Product List.
Vdet3 detection function, Vdet4 detection function,
cold start/warm start determination function
• Address space: 16 Mbytes
• External bus interface: 1 to 7 wait states can be inserted,
• Bus format: Switchable between separate bus and multiplexed
• Oscillation stop detection:
• Frequency divider circuit:
• Low power consumption features: Wait mode, stop mode
• Interrupt vectors: 70
• External interrupt inputs:
• Interrupt priority levels: 7
15-bit × 1 channel (with prescaler)
• 4 channels, cycle steal method
• Trigger sources: 31
• Transfer modes: 2 (single transfer and repeat transfer)
• Can be activated by all peripheral function interrupt sources
• Transfer modes: 2 (single transfer and burst transfer)
• Immediate transfer, calculation transfer, and chain transfer
16-bit timer × 5
16-bit timer × 6
3-phase inverter control × 1 (using timer A1, timer A2, timer A4,
and timer B2)
multiply-addition operation instructions: 16 × 16 + 48 → 48 bits)
4 chip select outputs, 3 V and 5 V interfaces
bus formats, switchable data bus width (8-bit or 16-bit)
Main clock, sub clock, on-chip oscillator,
PLL frequency synthesizer
Main clock oscillation stop detection function
Dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16
- 11 (NMI, INT × 6, Key input × 4) : 8-bit external bus width
- 8 (NMI, INT × 3, Key input × 4) : 16-bit external bus width
functions
31.3 ns ( f(CPU) = 32 MHz / VCC1 = 4.2 to 5.5 V)
41.7 ns ( f(CPU) = 24 MHz / VCC1 = 3.0 to 5.5 V)
Timer mode, event counter mode, one-shot timer mode,
pulse width modulation (PWM) mode
Event counter 2-phase pulse signal processing (2-phase
encoder input) × 3
Timer mode, event counter mode, pulse period measurement
mode, pulse width measurement mode
On-chip dead time timer
Specification
1. Overview