M308A5SGP#U5 Renesas Electronics America, M308A5SGP#U5 Datasheet - Page 61

• Manufacturer Part Number: M308A5SGP#U5
• Description: MCU ROMLESS 12K RAM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M308A5SGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 81
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 18x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M32C/8A Group
REJ03B0213-0111 Rev.1.11 Mar 31, 2009
Page 59 of 66
Timing Requirements
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.46
NOTE:
tac1(RD-DB)
tac1(AD-DB)
tac2(RD-DB)
tac2(AD-DB)
tsu(DB-BCLK)
tsu(RDY-BCLK)
tsu(HOLD-BCLK)
th(RD-DB)
th(BCLK-RDY)
th(BCLK-HOLD)
td(BCLK-HLDA)
1. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following
Symbol
equations. Insert wait states or lower the operation frequency, f(BCLK), if the calculated value is negative.
tac1(RD-DB) =
tac1(AD-DB) =
tac2(RD-DB) =
tac2(AD-DB) =
Microprocessor Mode
Data input access time (RD standard)
Data input access time (AD standard, CS standard)
Data input access time (RD standard, when accessing a space with the
multiplexed bus)
Data input access time (AD standard, when accessing a space with the
multiplexed bus)
Data input setup time
RDY input setup time
HOLD input setup time
Data input hold time
RDY input hold time
HOLD input hold time
HLDA output delay time
f(BCLK) × 2
f(BCLK) × 2
f(BCLK) × 2
10
10
10
10
f(BCLK)
9
9
9
9
× m
× n
× m
× p
- 35 [ns] (if external bus cycle is aφ + bφ, m = (b × 2) + 1)
- 35 [ns] (if external bus cycle is aφ + bφ, n = a + b)
- 35 [ns] (if external bus cycle is aφ + bφ, m = (b × 2) - 1)
- 35 [ns] (if external bus cycle is aφ + bφ, p = {(a + b - 1) × 2} + 1)
Parameter
VCC1 = VCC2 = 3.3 V
5. Electrical Characteristics
Min.
30
40
60
0
0
0
Standard
(note 1)
(note 1)
(note 1)
(note 1)
Max.
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns