M30280FCHP#U3B Renesas Electronics America, M30280FCHP#U3B Datasheet - Page 301

• Manufacturer Part Number: M30280FCHP#U3B
• Description: IC M16C/28 MCU FLASH 128K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FCHP#U3B

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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16.14 Precautions
e
E
1
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J
6
0
(1) Access to the registers of I
C
2
9
•S00 register
•S1D0 register
•S20 register
•S3D0 register
•S10 register
0 .
2 /
B
0
0
Do not rewrite the S20 register except the ACKBIT bit during transfer. If the bits in the S20 register
except ACKBIT bit are rewritten, the I
pletely.
Rewrite the ICK4 to ICK0 bits in the S3D0 register when the ES0 bit in the S1D0 register is set to "0"
(I
not use the bit managing instruction(read-modify-write instruction) to access the S3D0 register.
8
Do not use the bit managing instruction (read-modify-write instruction) because all bits in the S10
register will be changed, depending on the communication conditions. Do not read/write when te com-
munication mode select bits, the MST and TRX bits, are changing their value. Otherwise, data may be
read or written unsuccessfully. Figure16.21 to Figure 16.23 show the timing when the MST and TRX
bits change.
The following is precautions when read or write the control registers of I
Do not rewrite the S00 register during data transfer. If the bits in the S00 register are rewritten, the bit
counter for transfer is reset and data may not be transferred successfully.
The BC2 o BC0 bits are set to "0002" when START condition is detected or when 1-byte data transfer
is completed. Do not read or write the S1D0 register at this timing. Otherwise, data may be read or
written unsuccessfully. Figure 16.22 and Figure 16.23 show the bit counter reset timing.
0
2
4
G
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C bus interface is disabled). When the WIT bit is read, the internal WAIT flag is read. Therefore, do
7
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2
3
p
0
, 1
0
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M
2
0
1
0
6
7
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page 279
, 8
M
1
6
C
2
f o
2 /
C bus interface circuit
8
3
) B
8
5
2
C bus clock circuit is reset and data may be transferred incom-
16. MULTI-MASTER I
2
C bus interface circuit
2
C bus INTERFACE