R4F24568NVRFQV Renesas Electronics America, R4F24568NVRFQV Datasheet - Page 25

• Manufacturer Part Number: R4F24568NVRFQV
• Description: MCU 256KB FLASH 48K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24568NVRFQV

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.6 Processing of USB Standard Commands and Class/ Vendor Commands........................ 1008
16.7 Stall Operations................................................................................................................ 1009
16.8 DMA Transfer.................................................................................................................. 1012
16.9 Example of USB External Circuitry ................................................................................ 1015
16.10 Usage Notes ..................................................................................................................... 1017
Section 17 I
17.1 Features............................................................................................................................ 1021
17.2 Input/Output Pins............................................................................................................. 1023
17.3 Register Descriptions ....................................................................................................... 1024
16.5.2 Cable Connection.................................................................................................. 989
16.5.3 Cable Disconnection ............................................................................................. 990
16.5.4 Suspend and Resume Operations.......................................................................... 991
16.5.5 Control Transfer.................................................................................................... 998
16.5.6 EP1 Bulk-Out Transfer ....................................................................................... 1004
16.5.7 EP2 Bulk-In Transfer.......................................................................................... 1005
16.5.8 EP3 Interrupt-In Transfer.................................................................................... 1007
16.6.1 Processing of Commands Transmitted by Control Transfer............................... 1008
16.7.1 Overview ............................................................................................................ 1009
16.7.2 Forcible Stall by Application .............................................................................. 1009
16.7.3 Automatic Stall by USB Function Module ......................................................... 1011
16.8.1 Overview ............................................................................................................ 1012
16.8.2 Setting for the On-chip DMAC........................................................................... 1012
16.8.3 DMA Transfer for Endpoints 1 and 4 ................................................................. 1013
16.8.4 DMA Transfer for Endpoints 2........................................................................... 1014
16.10.1 Receiving Setup Data.......................................................................................... 1017
16.10.2 Clearing the FIFO ............................................................................................... 1017
16.10.3 Overreading and Overwriting the Data Registers ............................................... 1017
16.10.4 Assigning Interrupt Sources to EP0.................................................................... 1018
16.10.5 Clearing the FIFO When DMA Transfer is Enabled .......................................... 1018
16.10.6 Notes on TR Interrupt ......................................................................................... 1018
16.10.7 Module Stop Function Setting ............................................................................ 1019
17.3.1 I
17.3.2 I
17.3.3 I
17.3.4 I
17.3.5 I
17.3.6 Slave Address Register (SAR)............................................................................ 1035
17.3.7 I
17.3.8 I
2
2
2
2
2
2
2
2
C Bus Control Register A (ICCRA) ................................................................. 1026
C Bus Control Register B (ICCRB) ................................................................. 1028
C Bus Mode Register (ICMR).......................................................................... 1029
C Bus Interrupt Enable Register (ICIER)......................................................... 1031
C Bus Status Register (ICSR)........................................................................... 1033
C Bus Transmit Data Register (ICDRT) .......................................................... 1036
C Bus Receive Data Register (ICDRR)............................................................ 1036
C Bus Interface 2 (IIC2) ..............................................................1021
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