M30620FCPFP#U3C Renesas Electronics America, M30620FCPFP#U3C Datasheet - Page 207
![IC M16C MCU FLASH 100QFP](/photos/12/42/124208/m30620fcpfp_u3c_sml.jpg)
M30620FCPFP#U3C
Manufacturer Part Number
M30620FCPFP#U3C
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30620FCPFP#U3C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30620FCPFP#U3CM30620FCPFP#D3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Table 17.2
NOTES:
i=0 to 2
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
UiSMR
UiSMR2
UiSMR3
UiSMR4
UCON
Register
1. Set the bit 4 and bit 5 in the U0C1 and U1C1 register to “0”. The U0IRS, U1IRS, U0RRM and
2. TXD2 pin is N channel open-drain output. Set the NCH bit in the U2C0 register to “0”.
3. Not all register bits are described above. Set those bits to “0” when writing to the registers in clock
(3)
U1RRM bits in the UCON register.
synchronous serial I/O mode.
(3)
(3)
Jan 10, 2006
0 to 7
0 to 7
OER
0 to 7
SMD2 to SMD0
CKDIR
IOPOL
CLK1 to CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS
U2RRM
UiLCH
UiERE
0 to 7
0 to 7
0 to 2
NODC
4 to 7
0 to 7
U0IRS, U1IRS
U0RRM, U1RRM Set this bit to “1” to use continuous receive mode
CLKMD0
CLKMD1
RCSP
7
Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
(1)
Bit
(1)
Page 190 of 390
Set transmission data
Reception data can be read
Overrun error flag
Set a bit rate
Set to “001b”
Select the internal clock or external clock
Set to “0”
Select the count source for the UiBRG register
Select CTS or RTS to use
Transmit register empty flag
Enable or disable the CTS or RTS function
Select TXDi pin output mode
Select the transfer clock polarity
Select the LSB first or MSB first
Set this bit to “1” to enable transmission/reception
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select the source of UART2 transmit interrupt
Set this bit to “1” to use continuous receive mode
Set this bit to “1” to use inverted data logic
Set to “0”
Set to “0”
Set to “0”
Set to “0”
Select clock output mode
Set to “0”
Set to “0”
Select the source of UART0/UART1 transmit interrupt
Select the transfer clock output pin when CLKMD1 = 1
Set this bit to “1” to output UART1 transfer clock from two pins
Set this bit to “1” to accept as input the CTS0 signal of the UART0 from
the P6_4 pin
Set to “0”
(2)
Function
17. Serial Interface
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