M30620FCPFP#U3C Renesas Electronics America, M30620FCPFP#U3C Datasheet - Page 256
![IC M16C MCU FLASH 100QFP](/photos/12/42/124208/m30620fcpfp_u3c_sml.jpg)
M30620FCPFP#U3C
Manufacturer Part Number
M30620FCPFP#U3C
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30620FCPFP#U3C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30620FCPFP#U3CM30620FCPFP#D3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 18.5
A/D Control Register 1
A/D Control Register 0
b7 b6 b5 b4
NOTES :
b7 b6 b5 b4
NOTES :
1.
2.
1.
2.
3.
1
If the ADCON1 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate.
If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), w ait for 1 µs or more before starting
A/D conversion.
If the ADCON0 register is rew ritten during A/D conversion, the conversion result w ill be indeterminate.
AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same w ay as AN0 to AN7. Use the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register to select the desired pin. How ever, if VCC2 < VCC1, do not use AN0_0 to
AN0_7 and AN2_0 to AN2_7 as analog input pins.
After rew riting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using another instruction.
Jan 10, 2006
0
b3 b2 b1 b0
b3 b2 b1 b0
0
0
ADCON0 and ADCON1 Registers (One-shot Mode)
Bit Symbol
ADCON1
ADCON0
SCAN0
SCAN1
Symbol
Symbol
Symbol
CKS1
VCUT
OPA0
OPA1
ADST
CKS0
MD2
BITS
MD1
TRG
(1)
(1)
CH0
CH1
CH2
MD0
Page 239 of 390
A/D Sw eep Pin Select Bit
A/D Operation Mode Select Bit 1 Set to “0” w hen one-shot mode is selected
8/10-Bit Mode Select Bit
Frequency Select Bit 1
Vref Connect Bit
External Op-Amp Connection
Mode Bit
Analog Input Pin Select Bit
A/D Operation Mode Select
Bit 0
Trigger Select Bit
A/D Conversion Start Flag
Frequency Select Bit 0
(3)
Address
Address
Address
Bit Name
03D7h
03D6h
(2)
(2, 3)
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A/D converted
1 0 : ANEX1 input is A/D converted
1 1 : External op-amp connection mode
Invalid in one-shot mode
0 : 8-bit mode
1 : 10-bit mode
Refer to NOTE 3 for the ADCON2 Register
1 : Vref connected
b2 b1 b0
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
b4 b3
0 0 : One-shot mode
0 : Softw are trigger
1 : ADTRG
0 : A/D conversion disabled
1 : A/D conversion started
Refer to NOTE 3 for the ADCON2 Register
_________
trigger
After Reset
After Reset
00000XXXb
After Reset
Function
00h
18. A/D Converter
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
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