DF2268FA13 Renesas Electronics America, DF2268FA13 Datasheet - Page 231

• Manufacturer Part Number: DF2268FA13
• Description: IC H8S MCU FLASH 256K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2268FA13; HD64F2268FA13

2.2.59 (6)
SHLL (SHift Logical Left)
Operation
ERd (left logical shift)
Assembly-Language Format
SHLL.L #2, ERd
Operand Size
Longword
Description
This instruction shifts the bits in a 32-bit register ERd (destination operand) two bits to the left.
Bit 30 shifts into the carry flag. Bits 0 and 1 are cleared to 0.
Available Registers
ERd: ER0 to ER7
Operand Format and Number of States Required for Execution
Notes
The SHLL instruction differs from the SHAL instruction in its effect on the overflow flag.
Register direct
Addressing
Mode
SHLL (L)
Mnemonic
SHLL.L
C
ERd
MSB
Operands
b31
#2, ERd
b30
1st byte
1
. . . .
0
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Always cleared to 0.
C: Receives the previous value in bit 30.
2nd byte
7
Instruction Format
cleared to 0.
cleared to 0.
Rev. 4.00 Feb 24, 2006 page 215 of 322
—
I
0 erd
UI H
—
b1
0
Section 2 Instruction Descriptions
—
3rd byte
LSB
b0
0
—
U
N
0
4th byte
REJ09B0139-0400
Z
Shift Logical
V
0
States
No. of
C
1