HD6417760BP200AD Renesas Electronics America, HD6417760BP200AD Datasheet - Page 443
HD6417760BP200AD
Manufacturer Part Number
HD6417760BP200AD
Description
IC SUPERH MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BP200AD
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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HD6417760BP200AD
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HD6417760BP200AD
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D31
0
1
10.6.7
If the MD6 pin is cleared to 0 at a power-on reset by the RESET pin, the MPX interface is selected
for area 0. The MPX interface is selected for areas 1 to 6 by the MPX bit in BCR1 and bits
MEMMODE, A4MPX, and A1MPX in BCR3. The MPX interface provides an address/data
multiplex type bus protocol and allows easy connection with off-chip memory controller chips
using a single 32-bit address/data multiplex bus. A bus cycle consists of an address phase and a
data phase, with address information output to D25 to D0 and the access size output to D31 to D29
in the address phase. The BS signal is asserted for one cycle to indicate the address phase. The
CSn signal is asserted at the rising edge in Tm1 and is negated after the end of the last data
transfer in the data phase. Therefore, a negation cycle does not occur in the case of minimum pitch
access. The FRAME signal is asserted at the rising edge in Tm1 and negated at the start of the last
data transfer cycle in the data phase. Therefore, an off-chip device for the MPX interface must
internally store the address information and access size output in the address phase and perform
data input/output for the data phase. For details of access sizes and data alignment, see section
10.6.1, Endian/Access Size and Data Alignment.
Values output to address pins A25 to A20 are not guaranteed.
In 32-byte transfer, a total of 32 bytes are transferred consecutively according the bus width that
was set. The first access is performed on the data where there was an access request, and the
remaining accesses are performed on 32-byte boundary data. If the access size exceeds the set bus
width in this way, the address is output once, and then the burst access is performed with multiple
continuous data cycles. The bus is not released during this operation.
x: Don't care
MPX Interface
D30
0
1
x
x
D29
0
1
0
1
Access Size
Byte
Word
Longword
Quadword
32-byte burst
Rev. 2.00 Feb. 12, 2010 Page 359 of 1330
REJ09B0554-0200
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