HD6417760BP200AD Renesas Electronics America, HD6417760BP200AD Datasheet - Page 592

• Manufacturer Part Number: HD6417760BP200AD
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BP200AD

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

4. When the WDT count overflows, the CPG starts clock supply and the processor resumes
5. The counter stops at a value of H'00 to H'01. The value at which the counter stops depends on
13.3.2
The WDT is used when changing the clock frequency by means of the PLL. It is not used when
the frequency is changed simply by switching between frequency dividers.
1. Be sure to clear the TME bit in WTCSR to 0 before making a frequency change. If the TME
2. Select the count clock to be used with bits CKS2 to CKS0 in WTCSR, and set the initial value
3. When FRQCR is modified, the clock stops. The WDT starts counting. For details of FRQCR,
4. When the WDT count overflows, the CPG resumes clock supply and the processor resumes
5. The counter stops at a value of H'00 to H'01. The value at which the counter stops depends on
6. When re-setting WTCNT immediately after modifying FRQCR, first read the counter and
13.3.3
1. Set the WT/IT bit in WTCSR to 1, select the type of reset with the RSTS bit, and the count
2. When the TME bit in WTCSR is set to 1, the count starts in watchdog timer mode.
3. During operation in watchdog timer mode, write H'00 to the counter periodically so that it does
4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1, and generates a
Rev. 2.00 Feb. 12, 2010 Page 508 of 1330
REJ09B0554-0200
operation. The WOVF flag in WTCSR is not set at this time.
the clock ratio.
bit is set to 1, an inadvertent reset or interval timer interrupt may be caused when the count
overflows.
in WTCNT. Make these settings so that the time until the count overflows is at least as long as
the clock oscillation stabilization time.
see section 12.4.1, Frequency Control Register (FRQCR).
operation. The WOVF flag in WTCSR is not set at this time.
the clock ratio.
confirm that its value is as described in step 5 above.
clock with bits CKS2 to CKS0, and set the initial value in WTCNT.
not overflow.
reset of the type specified by the RSTS bit. The counter then continues counting.
Frequency Changing Procedure
Using Watchdog Timer Mode