SAK-XC864L-1FRI 5V AA Infineon Technologies, SAK-XC864L-1FRI 5V AA Datasheet - Page 43

• Manufacturer Part Number: SAK-XC864L-1FRI 5V AA
• Description: IC MCU 8BIT 4KB FLASH 20TSSOP
• Manufacturer: Infineon Technologies
• Series: XC8xxr

Specifications of SAK-XC864L-1FRI 5V AA

• Core Processor: XC800
• Core Size: 8-Bit
• Speed: 86MHz
• Connectivity: LIN, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3.3.3
In some applications, the Flash contents may need to be modified during program
execution. In-Application Programming (IAP) is supported so that users can program or
erase the Flash memory from their Flash user program by calling some special
subroutines. The Flash subroutines will first perform some checks and an initialization
sequence before starting the program or erase operation. A manual check on the Flash
data is necessary to determine if the programming or erasing was successful via using
the ‘MOVC’ instruction to read out the Flash contents. Other special subroutines include
aborting the Flash erase operation and checking the Flash bank ready-to-read status.
3.3.3.1
Each call of the Flash program subroutine allows the programming of 32 bytes of data
into the selected wordline (WL) of the Flash bank. Before calling the Flash program
subroutine, the user must ensure that required inputs
provided.
Flash Program Subroutine Type 1
If valid inputs have been set up, calling the subroutine begins flash programming. The
subroutine exits and returns to the user code, while the target Flash bank is still in
program mode, and is not accessible by user code.
The user code continues execution until the Flash NMI event is generated; bit
FNMIFLASH in register NMISR is set, and if enabled via NMIFLASH, an NMI to the CPU
is triggered to enter the Flash NMI service routine. At this point, the Flash bank is in
ready-to-read mode.
Table 14
Subroutine
Input
Output
Data Sheet
In-Application Programming
Flash Programming
Flash Program Subroutin Type 1
DFF6
DPTR (DPH, DPL
R0 of Register Bank 3 (IRAM address 18
IRAM start address for 32-byte Flash data
32-byte Flash data
Flash NMI (NMICON.NMIFLASH) is enabled (1) or disabled (0)
PSW.CY:
0 = Flash programming is in progress
1 = Flash programming is not started
Flag FNMIFLASH will be set when Flash programming has
successfully completed.
DPTR is incremented by 20
H
: FSM_PROG
1)
39
): Flash WL address
H
2)
(Table 14
Functional Description
H
):
and
Table
V 1.1, 2009-03
XC864
15) are