SAK-XC888-8FFA 5V AC Infineon Technologies, SAK-XC888-8FFA 5V AC Datasheet - Page 96
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SAK-XC888-8FFA 5V AC
Manufacturer Part Number
SAK-XC888-8FFA 5V AC
Description
IC MCU 8BIT FLASH 64-LQFP
Manufacturer
Infineon Technologies
Series
XC8xxr
Datasheet
1.SAF-XC888CLM-6FFA_5V_AC.pdf
(144 pages)
Specifications of SAK-XC888-8FFA 5V AC
Core Processor
XC800
Core Size
8-Bit
Speed
103.2MHz
Connectivity
SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.75K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-LFQFP
Data Bus Width
8 bit
Data Ram Size
1.75 KB
Interface Type
UART, SSC
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
B158-H8743-X-X-7600IN - KIT STARTER XC886/888
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
SP000210992
3.15
The UART module can be used to support the Local Interconnect Network (LIN) protocol
for both master and slave operations. The LIN baud rate detection feature, which
consists of the hardware logic for Break and Synch Byte detection, provides the
capability to detect the baud rate within LIN protocol using Timer 2. This allows the UART
to be synchronized to the LIN baud rate for data transmission and reception.
Note: The LIN baud rate detection feature is available for use only with UART. To use
LIN is a holistic communication concept for local interconnected networks in vehicles.
The communication is based on the SCI (UART) data format, a single-master/multiple-
slave concept, a clock synchronization for nodes without stabilized time base. An
attractive feature of LIN is self-synchronization of the slave nodes without a crystal or
ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the
baud rate must be calculated and returned with every message frame.
The structure of a LIN frame is shown in
•
•
•
•
Figure 31
3.15.1
LIN header transmission is only applicable in master mode. In the LIN communication,
a master task decides when and which frame is to be transferred on the bus. It also
identifies a slave task to provide the data transported by each frame. The information
Data Sheet
Header, which comprises a Break (13-bit time low), Synch Byte (55
Response time
Data bytes (according to UART protocol)
Checksum
UART1 for LIN communication, software has to be implemented to detect the
Break and Synch Byte.
LIN Protocol
LIN Header Transmission
Header
Structure of LIN Frame
Synch
Protected
identifier
Response
Frame slot
space
Frame
Data 1
Figure
89
Response
31. The frame consists of the:
Data 2
Data N
Functional Description
Checksum
XC886/888CLM
H
), and ID field
V1.2, 2009-07