UPD78F1142AGB-GAH-AX Renesas Electronics America, UPD78F1142AGB-GAH-AX Datasheet - Page 411
UPD78F1142AGB-GAH-AX
Manufacturer Part Number
UPD78F1142AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AGB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1142AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(2) Operation procedure
Cautions 1. After setting the PER0 register to 1, be sure to set the SPS0 register after 4 or more clocks
2. Be sure to set transmit data to the SlOp register before the clock from the master is
Changing setting of SOE0 register
Figure 11-63. Initial Setting Procedure for Slave Transmission/Reception
have elapsed.
started.
Starting communication
Setting SMR0n register
Setting SCR0n register
Setting SDR0n register
Writing to SS0 register
Setting PER0 register
Setting SPS0 register
Starting initial setting
Setting SO0 register
Setting port
CHAPTER 11 SERIAL ARRAY UNIT
User’s Manual U17854EJ9V0UD
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set bits 15 to 9 to 0000000B for baud
rate setting.
Manipulate the SO0n bit and set an
initial output level.
Set the SOE0n bit to 1 and enable data
output of the target channel.
Enable data output of the target channel
by setting a port register and a port
mode register.
SE0n = 1 when the SS0n bit of the target
channel is set to 1.
Set transmit data to the SIOp register
(bits 7 to 0 of the SDR0n register) and
wait for a clock from the master.
409
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