SAF-XC878CM-16FFI 3V3 AC Infineon Technologies, SAF-XC878CM-16FFI 3V3 AC Datasheet - Page 41
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SAF-XC878CM-16FFI 3V3 AC
Manufacturer Part Number
SAF-XC878CM-16FFI 3V3 AC
Description
IC MCU 8BIT 64KB FLASH 64LQFP
Manufacturer
Infineon Technologies
Series
XC8xxr
Specifications of SAF-XC878CM-16FFI 3V3 AC
Core Processor
XC800
Core Size
8-Bit
Speed
27MHz
Connectivity
CAN, SPI, SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
40
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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3.2.4
The SFRs of the XC87x are organized into groups according to their functional units. The
contents (bits) of the SFRs are summarized in
Note: The addresses of the bitaddressable SFRs appear in bold typeface.
3.2.4.1
The CPU SFRs can be accessed in both the standard and mapped memory areas
(RMAP = 0 or 1).
Table 5
Addr Register Name
RMAP = 0 or 1
81 H
82 H
83 H
87 H
88 H
89 H
8A H
8B H
8C H
8D H
94 H
95 H
96 H
Data Sheet
SP
Stack Pointer Register
DPL
Data Pointer Register Low
DPH
Data Pointer Register High
PCON
Power Control Register
TCON
Timer Control Register
TMOD
Timer Mode Register
TL0
Timer 0 Register Low
TL1
Timer 1 Register Low
TH0
Timer 0 Register High
TH1
Timer 1 Register High
MEX1
Memory Extension Register 1
MEX2
Memory Extension Register 2
MEX3
Memory Extension Register 3
XC87x Register Overview
CPU Registers
CPU Register Overview
Reset: 07 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Bit
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
SMOD
GATE
MCB1
DPH7
DPL7
MCM
TF1
rwh
rw
rw
rw
rw
rw
rw
7
1
9
34
DPH6
DPL6
TR1
T1S
rw
rw
rw
rw
6
Chapter 3.2.4.1
CB
0
r
r
DPH5
DPL5
MCB
TF0
rwh
rw
rw
rw
5
0
r
T1M
rw
DPH4
MXB1
DPL4
TR0
rw
rw
rw
rw
4
9
VAL
VAL
VAL
VAL
rwh
rwh
rwh
rwh
SP
rw
Functional Description
DPH3
GATE
DPL3
MXM
GF1
to
rwh
IE1
rw
rw
rw
rw
rw
3
0
Chapter
DPH2
DPL2
GF0
T0S
IT1
rw
rw
rw
rw
rw
2
NB
rw
rw
IB
XC87xCLM
V1.5, 2011-03
3.2.4.15.
DPH1
DPL1
MXB
rwh
IE0
rw
rw
rw
1
0
r
T0M
rw
DPH0
DPL0
IDLE
IT0
rw
rw
rw
rw
0
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