SAF-XC878CM-16FFI Infineon Technologies, SAF-XC878CM-16FFI Datasheet
SAF-XC878CM-16FFI
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SAF-XC878CM-16FFI Summary of contents
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XC878CLM 8-Bit Single-Chip Microcontroller Data Sheet V1.2 2009- ...
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... Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life ...
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XC878CLM 8-Bit Single-Chip Microcontroller Data Sheet V1.2 2009- ...
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XC878 Revision History: Previous Version: Page Subjects (major changes since last revision) Changes from V1.1 2009-08 to V1.2 2009-10 3 Table 1 and Table 2 has been updated to include the variants for the Automotive profile. 57 Table 21 has ...
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Data Sheet XC878CLM V1.2, 2009-11 ...
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Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Power-on Reset and PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.3.4 On-Chip Oscillator Characteristics ...
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Data Sheet I-4 XC878CLM Table of Contents V1.2, 2009-11 ...
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Single-Chip Microcontroller 1 Summary of Features The XC878 has the following features: • High-performance XC800 Core – compatible with standard 8051 processor – two clocks per machine cycle architecture (for memory access without wait state) – two data pointers ...
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... Synchronous serial channel (SSC) • On-chip debug support – 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM) – 64 bytes of monitor RAM • PG-LQFP-64 pin package • Temperature range T A – SAF (- °C) – SAX (-40 to 105 °C) Data Sheet : 2 XC878CLM Summary of Features V1.2, 2009-11 ...
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... Industrial), as shown in Table 2. Table 2 Device Profile Sales Type SAF-XC878-13FFI 5V SAF-XC878M-13FFI 5V SAF-XC878CM-13FFI 5V SAF-XC878-16FFI 5V SAF-XC878M-16FFI 5V SAF-XC878CM-16FFI 5V SAF-XC878-13FFI 3V3 SAF-XC878M-13FFI 3V3 SAF-XC878CM-13FFI 3V3 SAF-XC878-16FFI 3V3 SAF-XC878M-16FFI 3V3 Data Sheet CAN LIN BSL Module Support No No ...
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... Table 2 Device Profile (cont’d) Sales Type SAF-XC878CM-16FFI 3V3 SAX-XC878-13FFA 5V SAX-XC878CM-13FFA 5V SAX-XC878LM-13FFA 5V SAX-XC878CLM-13FFA 5V SAX-XC878-16FFA 5V SAX-XC878CM-16FFA 5V SAX-XC878LM-16FFA 5V SAX-XC878CLM-16FFA 5V As this document refers to all the derivatives, some description may not apply to a specific product. For simplicity, all versions are referred to by the term XC878 throughout this document ...
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General Device Information Chapter 2 contains the block diagram, pin configurations, definitions and functions of the XC878. 2.1 Block Diagram The block diagram of the XC878 is shown in XC878 8-Kbyte 1) Boot ROM 256-byte RAM + TMS 64-byte ...
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Logic Symbol The logic symbol of the XC878 is shown RESET MBC TMS XTAL1 XTAL2 Figure 3 XC878 Logic Symbol Data Sheet Figure V V DDP SSP AREF AGND XC878 DDC SSC 6 ...
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Pin Configuration The pin configuration of the XC878 P3.2 49 P3.3 50 P3.4 51 P3.5 52 RESET SSP V ...
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Pin Definitions and Functions The functions and default states of the XC878 external pins are provided in Table 3 Pin Definitions and Functions Symbol Pin Number (LQFP-64) P0 P0.0 17 P0.1 21 P0.2 18 P0.3 63 Data Sheet Type ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64) P0.4 64 P0.5 1 P0.6 2 P0.7 62 Data Sheet Type Reset Function State Hi-Z MTSR_1 CC62_1 TXD1_0 A18 Hi-Z MRST_1 EXINT0_0 T2EX1_1 RXD1_0 COUT62_1 A19 PU T2CC4_1 WR ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64) P1 P1.0 34 P1.1 35 P1.2 36 P1.3 37 P1.4 38 Data Sheet Type Reset Function State I/O Port 1 Port 8-bit bidirectional general purpose I/O ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64) P1.5 39 P1.6 10 P1.7 11 Data Sheet Type Reset Function State PU CCPOS0_1 EXINT5_0 T1_1 MRST_2 EXF2_0 RXDO_0 PU CCPOS1_1 T12HR_0 EXINT6_0 RXDC0_2 T21_1 PU CCPOS2_1 T13HR_0 T2_1 ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64) P3 P3.0 43 P3.1 44 P3.2 49 P3.3 50 Data Sheet Type Reset Function State I/O Port 3 Port 8-bit bidirectional general purpose I/O port. It ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64) P3.4 51 P3.5 52 P3.6 41 P3.7 42 Data Sheet Type Reset Function State Hi-Z CC62_0 RXDC0_1 T2EX1_0 T2CC3_1/ EXINT6_3 A14 Hi-Z COUT62_0 EXF21_0 TXDC0_1 A15 PU CTRAP_0 Hi-Z ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64) P4 P4.0 59 P4.1 60 P4.2 61 P4.3 40 P4.4 45 Data Sheet Type Reset Function State I/O Port 4 Port 8-bit bidirectional general purpose I/O ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64) P4.5 46 P4.6 47 P4.7 48 Data Sheet Type Reset Function State Hi-Z CCPOS1_3 T1_0 COUT61_2 T2CC3_0/ EXINT6_2 D5 Hi-Z CCPOS2_3 T2_0 CC62_2 T2CC4_0 D6 Hi-Z CTRAP_3 COUT62_2 T2CC5_0 ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64) P5 P5.0 8 P5.1 9 P5.2 12 P5.3 13 P5.4 14 Data Sheet Type Reset Function State I/O Port 5 Port 8-bit bidirectional general purpose I/O ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64) P5.5 15 P5.6 19 P5.7 20 Data Sheet Type Reset Function State PU CCPOS2_0 CTRAP_1 CC60_3 TDO_1 TXD1_2 T2CC0_2/ EXINT3_3 A5 PU TCK_1 RXDO1_2 T2CC1_2/ EXINT4_3 A6 PU TDI_1 ...
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Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64 25, 55 DDP V 26, 54 SSP V 6 DDC V 5 SSC V 32 AREF V 31 AGND AN0 22 AN1 23 AN2 24 AN3 27 ...
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Functional Description Chapter 3 provides an overview of the XC878 functional description. 3.1 Processor Architecture The XC878 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 ...
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Memory Organization The XC878 CPU operates in the following address spaces: • 8 Kbytes of Boot ROM program memory • 256 bytes of internal RAM data memory • 3 Kbytes of XRAM memory (XRAM can be read/written as program ...
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F’FFFF H Reserved 1'0000 H FFFF H External FEC0 H Reserved FE00 H External FC00 H XRAM 2 KByte F000 H D-Flash 4 KByte E000 H Boot ROM 8 KByte C000 H P-Flash 48 KByte / Reserved 8000 H P-Flash ...
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Memory Protection Strategy The XC878 memory protection strategy includes: • Basic protection: The user is able to block any external access via the boot option to any memory • Read-out protection: The user is able to protect the contents ...
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Table 4 Flash Protection Modes (cont’d) Flash Without hardware Protection protection P-Flash Possible program and erase D-Flash Read instructions in contents any program memory can be read by External Not possible access to D- Flash D-Flash Possible program D-Flash Possible ...
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Special Function Register The Special Function Registers (SFRs) occupy direct internal data memory space in the range All registers, except the program counter, reside in the SFR area. The H H SFRs include pointers and ...
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SFR Data (to/from CPU) Figure 8 Address Extension by Mapping Data Sheet Standard Area (RMAP = 0) Module 1 SFRs SYSCON0.RMAP Module 2 SFRs rw Module n SFRs Mapped Area (RMAP = 1) Module (n+1) SFRs Module (n+2) SFRs Module ...
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SYSCON0 System Control Register Field Bits RMAP [7:5], 3,1 Note: The RMAP bit should be cleared/set by ANL or ORL instructions.The rest bits of SYSCON0 should not be modified. 3.2.2.2 Address ...
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SFR Address (from CPU) SFR Data (to/from CPU) Figure 9 Address Extension by Paging In order to access a register located in a page different from the actual one, the current page must be exited. This is done by reprogramming ...
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Overwrite the contents of PAGE with the contents of STx, ignoring the value written to the bit positions of PAGE (this is done at the end of the interrupt routine to restore the previous page setting before the interrupt ...
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The page register has the following definition: MOD_PAGE Page Register for module MOD Field Bits PAGE [2:0] STNR [5:4] Data Sheet STNR Type Description rw Page Bits When written, the ...
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Field Bits OP [7: 3.2.3 Bit Protection Scheme The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11 bit field PASS opens access ...
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Password Register PASSWD Password Register 7 6 PASS Field Bits MODE [1:0] PROTECT_S 2 PASS [7:3] Data Sheet Type Description rw Bit Protection Scheme Control Bits 00 Scheme disabled - direct access to the protected ...
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XC878 Register Overview The SFRs of the XC878 are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in Note: The addresses of the bitaddressable SFRs appear in bold typeface. 3.2.4.1 CPU ...
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Table 5 CPU Register Overview (cont’d) Addr Register Name 97 H MEXSP Reset Memory Extension Stack Pointer Register 98 H SCON Reset Serial Channel Control Register 99 H SBUF Reset Serial Data Buffer Register ...
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Table 6 MDU Register Overview (cont’d) Addr Register Name B1 H MDUCON Reset MDU Control Register B2 H MD0 Reset MDU Operand Register MR0 Reset MDU Result Register ...
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Table 7 CORDIC Register Overview (cont’d) Addr Register Name 9C H CD_CORDYL Reset CORDIC Y Data Low Byte 9D H CD_CORDYH Reset CORDIC Y Data High Byte 9E H CD_CORDZL Reset CORDIC Z Data ...
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Table 8 SCU Register Overview (cont’d) Addr Register Name B7 H EXICON0 Reset External Interrupt Control Register EXICON1 Reset External Interrupt Control Register NMICON Reset NMI Control Register ...
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Table 8 SCU Register Overview (cont’d) Addr Register Name BB H PASSWD Reset Password Register BE H COCON Reset Clock Output Control Register E9 H MISC_CON Reset Miscellaneous Control Register EA H PLL_CON1 Reset: ...
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WDT Registers The WDT SFRs can be accessed in the mapped memory area (RMAP = 1). Table 9 WDT Register Overview Addr Register Name RMAP = WDTCON Reset Watchdog Timer Control Register BC H ...
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Table 10 Port Register Overview (cont’d) Addr Register Name B0 H P3_DATA Reset Data Register B1 H P3_DIR Reset Direction Register C8 H P4_DATA Reset Data Register C9 H P4_DIR Reset: ...
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Table 10 Port Register Overview (cont’d) Addr Register Name 91 H P1_ALTSEL1 Reset Alternate Select 1 Register 92 H P5_ALTSEL0 Reset Alternate Select 0 Register 93 H P5_ALTSEL1 Reset Alternate Select ...
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ADC Registers The ADC SFRs can be accessed in the standard memory area (RMAP = 0). Table 11 ADC Register Overview Addr Register Name RMAP = ADC_PAGE Reset Page Register RMAP = 0, PAGE ...
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Table 11 ADC Register Overview (cont’d) Addr Register Name RMAP = 0, PAGE ADC_RESR0L Reset Result Register 0 Low CB H ADC_RESR0H Reset Result Register 0 High CC H ADC_RESR1L Reset ...
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Table 11 ADC Register Overview (cont’d) Addr Register Name CB H ADC_RCR1 Reset Result Control Register ADC_RCR2 Reset Result Control Register ADC_RCR3 Reset Result Control Register 3 CE ...
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Table 11 ADC Register Overview (cont’d) Addr Register Name CC H ADC_CRMR1 Reset Conversion Request Mode Register ADC_QMR0 Reset Queue Mode Register ADC_QSR0 Reset Queue Status Register 0 ...
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Timer 2 Compare/Capture Unit Registers The Timer 2 Compare/Capture Unit SFRs can be accessed in the standard memory area (RMAP = 0). Table 12 T2CCU Register Overview Addr Register Name RMAP = T2_PAGE Reset ...
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Table 12 T2CCU Register Overview (cont’d) Addr Register Name C5 H T2CCU_CCTH Reset T2CCU Capture/Compare Timer Register High C6 H T2CCU_CCTCON Reset T2CCU CaptureCcompare Timer Control Register RMAP = 0, PAGE T2CCU_COSHDWReset: 00 ...
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Table 12 T2CCU Register Overview (cont’d) Addr Register Name RMAP = 0, PAGE T2CCU_CCTDTCLReset T2CCU Capture/Compare Timer Dead-Time Control Register Low C3 H T2CCU_CCTDTCHReset T2CCU Capture/Compare Timer Dead-Time Control Register High 3.2.4.9 Timer ...
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CCU6 Registers The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0). Table 14 CCU6 Register Overview Addr Register Name RMAP = CCU6_PAGE Reset Page Register RMAP = 0, PAGE ...
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Table 14 CCU6 Register Overview (cont’d) Addr Register Name FC H CCU6_CC61SRL Reset Capture/Compare Shadow Register for Channel CC61 Low FD H CCU6_CC61SRH Reset Capture/Compare Shadow Register for Channel CC61 High FE H CCU6_CC62SRL Reset: 00 ...
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Table 14 CCU6 Register Overview (cont’d) Addr Register Name FD H CCU6_CC61RH Reset Capture/Compare Register for Channel CC61 High FE H CCU6_CC62RL Reset Capture/Compare Register for Channel CC62 Low FF H CCU6_CC62RH Reset Capture/Compare ...
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Table 14 CCU6 Register Overview (cont’d) Addr Register Name FD H CCU6_MODCTRH Reset Modulation Control Register High FE H CCU6_TRPCTRL Reset Trap Control Register Low FF H CCU6_TRPCTRH Reset Trap Control Register High RMAP ...
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UART1 Registers The UART1 SFRs can be accessed in the mapped memory area (RMAP = 1). Table 15 UART1 Register Overview Addr Register Name RMAP = SCON Reset Serial Channel Control Register C9 H ...
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Table 16 SSC Register Overview (cont’d) Addr Register Name AB H SSC_CONH Reset Control Register High Operating Mode AC H SSC_TBL Reset Transmitter Buffer Register Low AD H SSC_RBL Reset Receiver Buffer Register Low ...
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Table 18 OCDS Register Overview Addr Register Name RMAP = MMCR2 Reset Monitor Mode Control 2 Register EA H MEXTCR Reset Memory Extension Control Register EB H MMWR1 Reset Monitor Work ...
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Flash Registers The Flash SFRs can be accessed in the mapped memory area (RMAP = 1). Table 19 Flash Register Overview Addr Register Name RMAP = FCON Reset P-Flash Control Register D2 H EECON ...
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Flash Memory The Flash memory provides an embedded user-programmable non-volatile memory, allowing fast and reliable storage of user code and data operated from a single 2.5 V supply from the Embedded Voltage Regulator (EVR) and does not ...
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Table 20 and Table 21 Industrial profile and Automotive profile respectively. Table 20 Flash Data Retention and Endurance for Industrial Profile (Operating Conditions apply) Retention Endurance Program Flash 15 years 1000 cycles Data Flash 15 years 1000 cycles 10 years ...
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Flash Bank Pagination The XC878 product family offers Flash devices with either 64 Kbytes or 52 Kbytes of embedded Flash memory. Each Flash device consists of a Program Flash (P-Flash) and a single Data Flash (D-Flash) bank. P-Flash has ...
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Interrupt System The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt requests. In addition to the standard interrupt functions supported by the core, e.g., configurable interrupt priority and interrupt masking, the XC878 interrupt system provides extended ...
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Timer 0 Overflow Timer 1 Overflow UART Receive UART Transmit EINT0 EXINT0 EXICON0.0/1 EINT1 EXINT1 EXICON0.2/3 Bit-addressable Request flag is cleared by hardware Figure 12 Interrupt Request Sources (Part 1) Data Sheet TF0 TCON.5 ET0 IEN0.1 TF1 TCON.7 ET1 IEN0.3 ...
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Timer 2 TF2 Overflow T2_T2CON.7 T2EX EXF2 T2_T2CON.6 EXEN2 T2_T2CON.3 EDGES EL CCT T2_T2MOD.5 Overflow T2CCU_CCTCON.3 Normal Divider Overflow End of Syn Byte Syn Byte Error MultiCAN Node 0 ADC Service Request 0 ADC Service Request 1 MultiCAN Node 1 ...
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SSC Error SSC Transmit SSC Receive EINT2 EXINT2 EXICON0.4/5 RI UART1_SCON.0 UART1 TI UART1_SCON.1 Timer 21 TF2 Overflow T21_T2CON.7 T21EX T21_T2CON.6 EXEN2 T21_T2CON.3 EDGES EL UART1 Normal T21_T2MOD.5 Divider Overflow CORDIC MDU Result Ready MDU Error addressable Request flag is ...
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T2CC0/ EINT3 EXINT3 EXICON0.6/7 T2CC1/ EINT4 EXINT4 EXICON1.0/1 T2CC2/ EINT5 EXINT5 EXICON1.2/3 T2CC3/ EINT6 EXINT6 EXICON1.4/5 Compare Channel 4 CM4F T2CCU_COCON.4 Compare Channel 5 CM5F T2CCU_COCON.5 MultiCAN Node 3 Bit- addressable Request flag is cleared by hardware Figure 15 Interrupt ...
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CCU6 Interrupt node 0 CCU6SR0 IRCON3.0 MultiCAN Node 4 CANSRC4 IRCON3.1 CCU6 Interrupt node 1 CCU6SR1 IRCON3.4 MultiCAN Node 5 CANSRC5 IRCON3.5 CCU6 Interrupt node 2 CCU6SR2 IRCON4.0 MultiCAN Node 6 CANSRC6 IRCON4.1 CCU6 Interrupt node 3 CCU6SRC3 IRCON4.4 MultiCAN ...
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Interrupt Source and Vector Each interrupt event source has an associated interrupt vector address for the interrupt node it belongs to. This vector is accessed to service the corresponding interrupt node request. The interrupt service of each interrupt source ...
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Table 22 Interrupt Vector Addresses (cont’d) Interrupt Vector Source Address XINTR6 0033 H XINTR7 003B H XINTR8 0043 H XINTR9 004B H XINTR10 0053 H XINTR11 005B H XINTR12 0063 H XINTR13 006B H Data Sheet Assignment for XC878 MultiCAN ...
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Interrupt Priority An interrupt that is currently being serviced can only be interrupted by a higher-priority interrupt, but not by another interrupt of the same or lower priority. Hence, an interrupt of the highest priority cannot be interrupted by ...
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Parallel Ports The XC878 has 40 port pins organized into five parallel ports: Port 0 (P0), Port 1 (P1), Port 3 (P3), Port 4 (P4) and Port 5 (P5). Each pin has a pair of internal pull-up and pull- ...
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Figure 17 shows the structure of a bidirectional port pin. Internal Bus Alternate Select Register 0 Alternate Select Register 1 AltDataOut 3 AltDataOut 2 AltDataOut1 AltDataIn Figure 17 General Structure of Bidirectional Port Data Sheet Px_PUDSEL Pull-up/Pull-down Select Register Pull-up/Pull-down ...
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Power Supply System with Embedded Voltage Regulator The XC878 microcontroller requires two different levels of power supply: • 3 5.0 V for the Embedded Voltage Regulator (EVR) and Ports • 2.5 V for the core, memory, on-chip ...
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Reset Control The XC878 has five types of reset: power-on reset, hardware reset, watchdog timer reset, power-down wake-up reset, and brownout reset. When the XC878 is first powered up, the status of certain pins (see defined to ensure proper ...
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Booting Scheme When the XC878 is reset, it must identify the type of configuration with which to start the different modes once the reset sequence is complete. Thus, boot configuration information that is required for activation of special modes ...
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... After the reset, the on-chip oscillator will be used by default.The external oscillator can be selected via software. In addition, the PLL provides a fail-safe logic to perform oscillator run and loss-of-lock detection. This allows emergency routines to be executed for system recovery or to perform system shut down. ...
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Wrapper PLL NR:1 OSC fosc OSCSS PDIV PLLPD Figure 19 CGU Block Diagram Direct Drive (PLL Bypass Operation) During PLL bypass operation, the system clock has the same frequency as the external clock source. PLL Mode The CPU clock is ...
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PLL mode. The PLL mode is used during normal system operation. System Frequency Selection For the XC878, the value of NF, NR and OD can be selected by bits NDIV, PDIV and KDIV respectively for ...
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Oscillation measurement with the final target system is strongly recommended to verify the input amplitude at XTAL1 and to determine the actual oscillation allowance (margin negative resistance) for the oscillator-crystal system. When using an external clock signal, the ...
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Clock Management The CGU generates all clock signals required within the microcontroller from a single f clock, . During normal system operation, the typical frequencies of the different sys modules are as follow: • CPU clock: CCLK, SCLK = ...
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OSCSS External fosc OSC PLL On-chip OSC NF,NR,OD Figure 21 Clock Generation from Data Sheet CCCFG CORDIC CLK CORDIC MDUCCFG MDU CLK MDU CLKREL SD 1 FCLK /2 fsys 0 /3 COREL TLEN Toggle Latch f sys 78 XC878CLM Functional ...
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For power saving purposes, the clocks may be disabled or slowed down according to Table 27. Table 27 System frequency ( Power Saving Mode Action Idle Clock to the CPU is disabled. Slow-down Clocks to the CPU and all the ...
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Power Saving Modes The power saving modes of the XC878 provide flexible power consumption through a combination of techniques, including: • Stopping the CPU clock • Stopping the clocks of individual system components • Reducing clock speed of some ...
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Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failures. The WDT is reset at a regular interval that is predefined by the user. The CPU must ...
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If the WDT is not serviced before the timer overflow, a system malfunction is assumed result, the WDT NMI is triggered (assert FNMIWDT) and the reset prewarning is entered. The prewarning period lasts for 30 (assert WDTRST). The ...
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FFFF H WDTWINB WDTREL Figure 24 WDT Timing Diagram Table 28 lists the possible watchdog time ranges that can be achieved using a certain module clock. Some numbers are rounded to 3 significant digits. Table 28 Watchdog Time Ranges Reload ...
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Multiplication/Division Unit The Multiplication/Division Unit (MDU) provides fast 16-bit multiplication, 16-bit and 32-bit division as well as shift and normalize features. It has been integrated to support the XC878 Core in real-time control applications, which require fast mathematical computations. ...
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CORDIC Coprocessor The CORDIC Coprocessor provides CPU with hardware support for the solving of circular (trigonometric), linear (multiply-add, divide-add) and hyperbolic functions. Features • Modes of operation – Supports all CORDIC operating modes for solving circular (trigonometric), linear (multiply-add, ...
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Interrupt enabling and corresponding flag 3.13 UART and UART1 The XC878 provides two Universal Asynchronous Receiver/Transmitter (UART and UART1) modules for full-duplex asynchronous reception/transmission. Both are also receive-buffered, i.e., they can commence reception of a second byte before a ...
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Figure 25. FDM FDEN f f PCLK DIV Prescaler clk Figure 25 Baud-rate Generator Circuitry The baud rate timer is a count-down timer and ...
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The following formulas calculate the final baud rate without and with the fractional divider respectively: baud rate ---------------------------------------------------------------------------------- - where 2 = BRPRE × baud rate The maximum baud rate that can be generated is limited to clock ...
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Table 32 Deviation Error for UART with Fractional Divider enabled f Prescaling Factor PCLK (2BRPRE) 24 MHz 1 12 MHz 1 8 MHz 1 6 MHz 1 3.13.2 Baud Rate Generation using Timer 1 In UART modes 1 and 3 ...
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LIN Protocol The UART module can be used to support the Local Interconnect Network (LIN) protocol for both master and slave operations. The LIN baud rate detection feature, which consists of the hardware logic for Break and Synch Byte ...
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The header consists of a break and synch pattern followed by an identifier. Among these three fields, ...
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High-Speed Synchronous Serial Interface The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be received ...
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PCLK Baud-rate Generator Transmit Buffer Register TB Figure 27 SSC Block Diagram Data Sheet Clock Control Shift Clock RIR TIR SSC Control Block Register CON EIR Status Control Pin 16-Bit Shift Control Register Receive Buffer Register RB Internal Bus 93 ...
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Timer 0 and Timer 1 Timer 0 and Timer 1 can function as both timers or counters. When functioning as a timer, Timer 0 and Timer 1 are incremented every machine cycle, i.e. every 2 input clocks (or 2 ...
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Timer 2 and Timer 21 Timer 2 and Timer 21 are 16-bit general purpose timers (THL2) that are fully compatible and have two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel capture mode, see Table ...
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Timer 2 Capture/Compare Unit The T2CCU (Timer 2 Capture/Compare Unit) consists of the standard Timer 2 unit and a Capture/compare unit (CCU). The Capture/Compare Timer (CCT) is part of the CCU. Control is available in the T2CCU to select ...
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Capture/Compare Unit 6 The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor control. The CCU6 also supports special control modes for block commutation and ...
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T12 clock control start T13 interrupt control Figure 28 CCU6 Block Diagram Data Sheet module kernel compare channel 0 1 dead- channel 1 time 1 control channel 2 1 channel 3 compare input / output ...
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Controller Area Network (MultiCAN) The MultiCAN module contains two Full-CAN nodes operating independently or exchanging data and remote frames via a gateway function. Transmission and reception of CAN frames is handled in accordance to CAN specification V2.0 B active. ...
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CAN functionality according to CAN specification V2.0 B active. • Dedicated control registers are provided for each CAN node. • A data transfer rate MBaud is supported. • Flexible and powerful message transfer control and error ...
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Analog-to-Digital Converter The XC878 includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with eight multiplexed analog input channels. The ADC uses a successive approximation technique to convert the analog voltage levels from up to eight different sources. The analog input ...
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ADC f ADCA Figure 30 ADC Clocking Scheme f For module clock = 24 MHz, the analog clock ADC shown in Table 35. f Table 35 Frequency Selection ADCI f Module Clock CTC ADC 24 MHz 00 ...
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Synchronization phase ( t • Sample phase ( ) S • Conversion phase t • Write result phase ( WR conversion start trigger Sample Phase f ADCI BUSY Bit SAMPLE Bit t SYN Figure 31 ADC Conversion Timing Data ...
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On-Chip Debug Support The On-Chip Debug Support (OCDS) provides the basic functionality required for the software development and debugging of XC800-based systems. The OCDS design is based on these principles: • Use the built-in debug functionality of the XC800 ...
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JTAG Module TMS TCK Debug JTAG TDI Interface TDO MBC Monitor & Bootstrap loader Control line Suspend Control System Control Reset Unit Clock - parts of OCDS Figure 32 OCDS Block Diagram 3.23.1 JTAG ID Register This is a read-only ...
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Chip Identification Number The XC878 identity (ID) register is located at Page 1 of address B3 register However, for easy identification of product variants, the Chip H Identification Number, which is an unique number assigned to ...
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Electrical Parameters Chapter 4 provides the characteristics of the electrical parameters which are implementation-specific for the XC878. 4.1 General Parameters The general parameters are described here to aid the users in interpreting the parameters mainly in Section 4.2 4.1.1 ...
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Absolute Maximum Rating Maximum ratings are the extreme limits to which the XC878 can be subjected to without permanent damage. Table 38 Absolute Maximum Rating Parameters Parameter Ambient temperature Storage temperature Junction temperature Voltage on power supply pin with ...
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... CCLK Data Sheet Symbol Limit Values min. max. V 4.5 5.5 DDP V 3.0 3.6 DDP 26.67 CCLK T - -40 105 Figure 21 110 XC878CLM Electrical Parameters Unit Notes/ Conditions V 5V Device V 3.3V Device V 2) MHz °C SAF-XC878 °C SAX-XC878 for detailed description. V1.2, 2009-11 ...
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DC Parameters The electrical characteristics of the DC Parameters are detailed in this section. 4.2.1 Input/Output Characteristics Table 40 provides the characteristics of the input/output pins of the XC878. Table 40 Input/Output Characteristics (Operating Conditions apply) Parameter Symbol V ...
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Table 40 Input/Output Characteristics (Operating Conditions apply) (cont’d) Parameter Symbol I Maximum current per V pin (excluding DDP V and ) SS Σ| Maximum current for all pins (excluding V V and ) DDP SS I Maximum current into V ...
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Table 40 Input/Output Characteristics (Operating Conditions apply) (cont’d) Parameter Symbol V Voltage on any pin V during power off DDP I Maximum current per V pin (excluding DDP V and ) SS Σ| Maximum current for all pins (excluding V ...
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Supply Threshold Characteristics Table 41 provides the characteristics of the supply threshold in the XC878. 5.0V VDDP 2.5V VDDC V DDCPOR Figure 33 Supply Threshold Parameters Table 41 Supply Threshold Parameters (Operating Conditions apply) Parameters 1) V brownout voltage ...
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ADC Characteristics The values in the table below are given for an analog power supply between 4 5.5 V. The ADC can be used with an analog power supply down But in this case, ...
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Table 42 ADC Characteristics (Operating Conditions apply; Parameter Symbol R Input resistance of AREF the reference input R Input resistance of AIN the selected analog channel 1) Not subjected to production test, verified by design/characterization. 2) This value includes the ...
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R EXT V C AIN EXT V AREF Figure 34 ADC Input Circuits Data Sheet R AIN, On ANx V AGNDx Reference Voltage Input Circuitry R V AREF, On AREFx V AGNDx 117 XC878CLM Electrical Parameters Analog Input Circuitry C ...
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ADC Conversion Timing t t Conversion time ADC r = CTC + 2 for CTC = for CTC = CTC = Conversion Time Control (GLOBCTR.CTC), STC = Sample Time Control ...
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Power Supply Current Table 43, Table 44, Table 45 supply current in the XC878. Table 43 Power Supply Current Parameters (Operating Conditions apply range) DDP Parameter Range DDP Active Mode Idle Mode Active ...
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Table 44 Power Down Current (Operating Conditions apply; Parameter Range DDP Power-Down Mode I 1) The typical values are based on preliminary measurements and are to be used as reference only. These PDP V values are measured ...
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Table 45 Power Supply Current Parameters (Operating Conditions apply 3.3V range) DDP Parameter V = 3.3V Range DDP Active Mode Idle Mode Active Mode with slow-down enabled Idle Mode with slow-down enabled I 1) The typical values are ...
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Table 46 Power Down Current (Operating Conditions apply; range) Parameter V = 3.3V Range DDP Power-Down Mode I 1) The typical values are based on preliminary measurements and are to be used as reference only. These PDP V values are ...
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AC Parameters The electrical characteristics of the AC Parameters are detailed in this section. 4.3.1 Testing Waveforms The testing waveforms for rise/fall time, output delay and output high impedance are shown in Figure 35, Figure 36 V DDP 10% ...
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Output Rise/Fall Times Table 47 provides the characteristics of the output rise/fall times in the XC878. Table 47 Output Rise/Fall Times Parameters (Operating Conditions apply) Parameter Range DDP Rise/fall times V = 3.3V Range DDP Rise/fall ...
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Power-on Reset and PLL Timing Table 53 provides the characteristics of the power-on reset and PLL timing in the XC878. Table 48 Power-On Reset and PLL Timing (Operating Conditions apply) Parameter Symbol t On-Chip Oscillator start-up time t PLL ...
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On-Chip Oscillator Characteristics Table 49 provides the characteristics of the on-chip oscillator in the XC878. Table 49 On-chip Oscillator Characteristics (Operating Conditions apply) Parameter Symbol f Nominal frequency NOM ∆ f Long term frequency LT deviation ∆ f Short ...
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External Data Memory Characteristics Table 50 shows the timing of the external data memory read cycle. Table 50 External Data Memory Read Timing (Operating Conditions apply) Parameter Symbol t RD pulse width t Address valid ...
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Table 51 shows the timing of the external data memory write cycle. Table 51 External Data Memory Write Timing (Operating Conditions apply) Parameter WR pulse width Address valid to WR Data valid to WR transition Data setup before WR Data ...
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External Clock Drive XTAL1 Table 52 shows the parameters that define the external clock supply for XC878. These timing parameters are based on the direct XTAL1 drive of clock input signals. They are not applicable if an external crystal ...
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JTAG Timing Table 53 provides the characteristics of the JTAG timing in the XC878. Table 53 TCK Clock Timing (Operating Conditions apply pF) Parameter TCK clock period TCK high time TCK low time TCK clock rise ...
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Table 54 JTAG Timing (Operating Conditions apply pF) (cont’d) Parameter TDO high impedance to valid output from TCK TDO valid output to high impedance from TCK 1) Not all parameters are 100% tested, but are verified by ...
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SSC Master Mode Timing Table 55 provides the characteristics of the SSC timing in the XC878. Table 55 SSC Master Mode Timing (Operating Conditions apply pF) Parameter SCLK clock period MTSR delay from SCLK MRST setup ...
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Data Sheet Electrical Parameters 133 XC878CLM V1.2, 2009-11 ...
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Package and Quality Declaration Chapter 5 provides the information of the XC878 package and reliability section. 5.1 Package Parameters Table 1 provides the thermal characteristics of the PG-LQFP-64-4 package used in XC878. Table 1 Thermal Characteristics of the Packages ...
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Package Outline Figure 45 shows the package outlines of the XC878. Figure 45 PG-LQFP-64-4 Package Outline Data Sheet Package and Quality Declaration 134 XC878CLM V1.2, 2009-11 ...
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Quality Declaration Table 2 shows the characteristics of the quality parameters in the XC878. Table 2 Quality Parameters Parameter ESD susceptibility according to Human Body Model (HBM) ESD susceptibility according to Charged Device Model (CDM) pins Data Sheet Package ...
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Data Sheet Package and Quality Declaration 136 XC878CLM V1.2, 2009-11 ...
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... Published by Infineon Technologies AG ...