UPD78F1144AF1-BA4-A Renesas Electronics America, UPD78F1144AF1-BA4-A Datasheet - Page 439
UPD78F1144AF1-BA4-A
Manufacturer Part Number
UPD78F1144AF1-BA4-A
Description
MCU 16BIT 78K0R/KX3 64-FBGA
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1144AF1-BA4-A
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 439 of 880
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11.6.3 LIN transmission
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
designed to reduce the cost of an automobile network.
receives this frame and corrects a baud rate error from the master. If the baud rate error of a slave is within ±15%,
communication can be established.
Remark f
Support of LIN communication
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Parity bit
Stop bit
Data direction
Of UART transmission, UART3 supports LIN communication.
For LIN transmission, channel 2 of unit 1 (SAU1) is used.
LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol
Communication of LIN is single-master communication and up to 15 slaves can be connected to one master.
The slaves are used to control switches, actuators, and sensors, which are connected to the master via LIN.
Usually, the master is connected to a network such as CAN (Controller Area Network).
A LIN bus is a single-wire bus to which nodes are connected via transceiver conforming to ISO9141.
According to the protocol of LIN, the master transmits a frame by attaching baud rate information to it. A slave
Figure 11-85 outlines a transmission operation of LIN.
specifications (see CHAPTER 27
CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
f
MCK
CLK
UART
: System clock frequency
: Operation clock (MCK) frequency of target channel
Not supported
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer
mode) can be selected.
None
8 bits
Max. f
Reverse output (default: low level)
• No parity bit
• Appending 0 parity
• Appending even parity
• Appending odd parity
The following selectable
• Appending 1 bit
• Appending 2 bits
MSB or LSB first
Forward output (default: high level)
The following selectable
MCK
/6 [bps] (SDR12 [15:9] = 2 or more), Min. f
CHAPTER 11 SERIAL ARRAY UNIT
UART0
−
−
−
User’s Manual U17854EJ9V0UD
ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) and
Not supported
UART1
−
−
−
CLK
/(2 × 2
11
× 128) [bps]
Supported
Channel 2 of SAU1
TxD3
INTST3
Note
UART3
437
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