SAK-XC2236N-24F40L Infineon Technologies, SAK-XC2236N-24F40L Datasheet - Page 15
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SAK-XC2236N-24F40L
Manufacturer Part Number
SAK-XC2236N-24F40L
Description
IC MCU 16BIT FLASH 64-LQFP
Manufacturer
Infineon Technologies
Series
XC22xxNr
Specifications of SAK-XC2236N-24F40L
Core Processor
C166SV2
Core Size
16/32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
Peripherals
I²S, POR, PWM, WDT
Number Of I /o
40
Program Memory Size
192KB (192K x 8)
Program Memory Type
FLASH
Ram Size
26K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
SP000527770
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SAK-XC2236N-24F40L
Manufacturer:
Infineon Technologies
Quantity:
10 000
Company:
Part Number:
SAK-XC2236N-24F40L AA
Manufacturer:
Infineon Technologies
Quantity:
10 000
Key to Pin Definitions
•
•
Table 6
Pin
3
4
5
Data Sheet
Ctrl.: The output signal for a port pin is selected by bit field PC in the associated
register Px_IOCRy. Output O0 is selected by setting the respective bit field PC to
1x00
Output signal OH is controlled by hardware.
Type: Indicates the pad type and its power supply domain (A, B, M, 1).
– St: Standard pad
– Sp: Special pad e.g. XTALx
– DP: Double pad - can be used as standard or high speed pad
– In: Input only pad
– PS: Power supply pad
Symbol
TESTM
TRST
P7.0
T3OUT
T6OUT
TDO_A
ESR2_1
RxDC4B
B
, output O1 is selected by 1x01
Pin Definitions and Functions
Ctrl.
I
I
O0 / I St/B
O1
O2
OH /
IH
I
I
Type Function
In/B
In/B
St/B
St/B
St/B
St/B
St/B
Testmode Enable
Enables factory test modes, must be held HIGH for
normal operation (connect to
An internal pull-up device will hold this pin high
when nothing is driving it.
Test-System Reset Input
For normal system operation, pin TRST should be
held low. A high level at this pin at the rising edge
of PORST activates the XC223xN’s debug
system. In this case, pin TRST must be driven low
once to reset the debug system.
An internal pull-down device will hold this pin low
when nothing is driving it.
Bit 0 of Port 7, General Purpose Input/Output
GPT12E Timer T3 Toggle Latch Output
GPT12E Timer T6 Toggle Latch Output
JTAG Test Data Output / DAP1 Input/Output
If DAP pos. 0 or 2 is selected during start-up, an
internal pull-down device will hold this pin low
when nothing is driving it.
ESR2 Trigger Input 1
CAN Node 4 Receive Data Input
XC2232N, XC2234N, XC2236N, XC2238N
B
, etc.
15
XC2000 Family / Value Line
General Device Information
V
DDPB
).
V1.3, 2010-04