SAK-XC2236N-24F40L Infineon Technologies, SAK-XC2236N-24F40L Datasheet - Page 37
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SAK-XC2236N-24F40L
Manufacturer Part Number
SAK-XC2236N-24F40L
Description
IC MCU 16BIT FLASH 64-LQFP
Manufacturer
Infineon Technologies
Series
XC22xxNr
Specifications of SAK-XC2236N-24F40L
Core Processor
C166SV2
Core Size
16/32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
Peripherals
I²S, POR, PWM, WDT
Number Of I /o
40
Program Memory Size
192KB (192K x 8)
Program Memory Type
FLASH
Ram Size
26K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
SP000527770
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SAK-XC2236N-24F40L
Manufacturer:
Infineon Technologies
Quantity:
10 000
Company:
Part Number:
SAK-XC2236N-24F40L AA
Manufacturer:
Infineon Technologies
Quantity:
10 000
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Functional Description
to a dedicated vector table location). The occurrence of a hardware trap is also indicated
by a single bit in the trap flag register (TFR). Unless another higher-priority trap service
is in progress, a hardware trap will interrupt any ongoing program execution. In turn,
hardware trap services can normally not be interrupted by standard or PEC interrupts.
Depending on the package option up to 3 External Service Request (ESR) pins are
provided. The ESR unit processes their input values and allows to implement user
controlled trap functions (System Requests SR0 and SR1). In this way reset, wakeup
and power control can be efficiently realized.
Software interrupts are supported by the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number. Alternatively to emulate an interrupt by software a
program can trigger interrupt requests by writing the Interrupt Request (IR) bit of an
interrupt control register.
3.6
On-Chip Debug Support (OCDS)
The On-Chip Debug Support system built into the XC223xN provides a broad range of
debug and emulation features. User software running on the XC223xN can be debugged
within the target system environment.
The OCDS is controlled by an external debugging device via the debug interface. This
either consists of the 2-pin Device Access Port (DAP) or of the JTAG port conforming to
IEEE-1149. The debug interface can be completed with an optional break interface.
The debugger controls the OCDS with a set of dedicated registers accessible via the
debug interface (DAP or JTAG). In addition the OCDS system can be controlled by the
CPU, e.g. by a monitor program. An injection interface allows the execution of OCDS-
generated instructions by the CPU.
Multiple breakpoints can be triggered by on-chip hardware, by software, or by an
external trigger input. Single stepping is supported, as is the injection of arbitrary
instructions and read/write access to the complete internal address space. A breakpoint
trigger can be answered with a CPU halt, a monitor call, a data transfer, or/and the
activation of an external signal.
Tracing of data can be obtained via the debug interface, or via the external bus interface
for increased performance.
Tracing of program execution is supported by the XC2000 Family emulation device. With
this device the DAP can operate on clock rates of up to 20 MHz.
The DAP interface uses two interface signals, the JTAG interface uses four interface
signals, to communicate with external circuitry. The debug interface can be amended
with two optional break lines.
Data Sheet
37
V1.3, 2010-04