SAF-XE164G-24F66L AC Infineon Technologies, SAF-XE164G-24F66L AC Datasheet - Page 40

• Manufacturer Part Number: SAF-XE164G-24F66L AC
• Description: IC MCU 16BIT FLASH 100-LQFP
• Manufacturer: Infineon Technologies
• Series: XE16xr

Specifications of SAF-XE164G-24F66L AC

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
• Peripherals: I²S, POR, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 192KB (192K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: SP000363795

3.4
With a minimum interrupt response time of 7/11
program execution), the XE164 can react quickly to the occurrence of non-deterministic
events.
The architecture of the XE164 supports several mechanisms for fast and flexible
response to service requests; these can be generated from various sources internal or
external to the microcontroller. Any of these interrupt requests can be programmed to be
serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).
Where in a standard interrupt service the current program execution is suspended and
a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the
current CPU activity to perform a PEC service. A PEC service implies a single byte or
word data transfer between any two memory locations with an additional increment of
either the PEC source pointer, the destination pointer, or both. An individual PEC
transfer counter is implicitly decremented for each PEC service except when performing
in the continuous transfer mode. When this counter reaches zero, a standard interrupt is
performed to the corresponding source-related vector location. PEC services are
particularly well suited to supporting the transmission or reception of blocks of data. The
XE164 has eight PEC channels, each whith fast interrupt-driven data transfer
capabilities.
Each of the possible interrupt nodes has a separate control register containing an
interrupt request flag, an interrupt enable flag and an interrupt priority bitfield. Each node
can be programmed by its related register to one of sixteen interrupt priority levels. Once
accepted by the CPU, an interrupt service can only be interrupted by a higher-priority
service request. For standard interrupt processing, each possible interrupt node has a
dedicated vector location.
Fast external interrupt inputs can service external interrupts with high-precision
requirements. These fast interrupt inputs feature programmable edge detection (rising
edge, falling edge, or both edges).
Software interrupts are supported by the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.
Table 6
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.
Note: Interrupt nodes which are not assigned to peripherals (unassigned nodes) may be
1) Depending if the jump cache is used or not.
Data Sheet
used to generate software-controlled interrupt requests by setting the respective
interrupt request bit (xIR).
shows all of the possible XE164 interrupt sources and the corresponding
Interrupt System
38
1)
CPU clocks (in the case of internal
XE166 Family Derivatives
Functional Description
V2.1, 2008-08
XE164x