SAK-XC2785X-104F80L AA Infineon Technologies, SAK-XC2785X-104F80L AA Datasheet - Page 120

no-image

SAK-XC2785X-104F80L AA

Manufacturer Part Number
SAK-XC2785X-104F80L AA
Description
IC MCU 32BIT FLASH 144-LQFP
Manufacturer
Infineon Technologies
Series
XC27x5Xr
Datasheet

Specifications of SAK-XC2785X-104F80L AA

Core Processor
C166SV2
Core Size
16/32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
Peripherals
I²S, POR, PWM, WDT
Number Of I /o
116
Program Memory Size
832KB (832K x 8)
Program Memory Type
FLASH
Ram Size
50K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LFQFP
Data Bus Width
16 bit, 32 bit
Data Ram Size
32 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
119
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
SP000439080
Figure 24
Note: If the READY input is sampled inactive at the indicated sampling point (“Not Rdy”)
Data Sheet
CLKOUT
RD, WR
D15-D0
(read)
D15-D0
(write)
READY
Synchronous
READY
Asynchron.
a READY-controlled waitstate is inserted (tpRDY),
sampling the READY input active at the indicated sampling point (“Ready”)
terminates the currently running bus cycle.
Note the different sampling points for synchronous and asynchronous READY.
This example uses one mandatory waitstate (see tpE) before the READY input
value is used.
READY Timing
tp
D
t
10
Not Rdy READY
t
30
t
31
tp
XC2000 Family Derivatives / Base Line
120
E
Data Out
Not Rdy
t
t
30
30
t
31
tp
t
RDY
31
Data In
t
READY
30
t
30
Electrical Parameters
t
tp
20
MC_X_EBCREADY
t
31
F
t
31
V2.0, 2009-03
XC2785X
t
25

Related parts for SAK-XC2785X-104F80L AA