SAK-XC2785X-104F80L AA Infineon Technologies, SAK-XC2785X-104F80L AA Datasheet - Page 29

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SAK-XC2785X-104F80L AA

Manufacturer Part Number
SAK-XC2785X-104F80L AA
Description
IC MCU 32BIT FLASH 144-LQFP
Manufacturer
Infineon Technologies
Series
XC27x5Xr
Datasheet

Specifications of SAK-XC2785X-104F80L AA

Core Processor
C166SV2
Core Size
16/32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
Peripherals
I²S, POR, PWM, WDT
Number Of I /o
116
Program Memory Size
832KB (832K x 8)
Program Memory Type
FLASH
Ram Size
50K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LFQFP
Data Bus Width
16 bit, 32 bit
Data Ram Size
32 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
119
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
SP000439080
Table 5
Pin
90
92
93
94
Data Sheet
Symbol
P0.4
U1C1_SELO
0
U1C0_SELO
1
CCU61_COU
T61
A4
U1C1_DX2A
RxDC1B
ESR2_8
P2.13
U2C1_SELO
2
P3.2
U2C0_SCLK
OUT
U2C0_DX1B
HOLD
P2.10
U0C1_DOUT O1
U0C0_SELO
3
CC2_CC23
A23
U0C1_DX0E
CAPINA
Pin Definitions and Functions (cont’d)
Ctrl.
O0 / I St/B
O1
O2
O3
OH
I
I
I
O0 / I St/B
O1
O0 / I St/B
O1
I
I
O0 / I St/B
O2
O3 / I St/B
OH
I
I
Type Function
St/B
St/B
St/B
St/B
St/B
St/B
St/B
St/B
St/B
St/B
St/B
St/B
St/B
St/B
St/B
St/B
Bit 4 of Port 0, General Purpose Input/Output
USIC1 Channel 1 Select/Control 0 Output
USIC1 Channel 0 Select/Control 1 Output
CCU61 Channel 1 Output
External Bus Interface Address Line 4
USIC1 Channel 1 Shift Control Input
CAN Node 1 Receive Data Input
ESR2 Trigger Input 8
Bit 13 of Port 2, General Purpose Input/Output
USIC2 Channel 1 Select/Control 2 Output
Bit 2 of Port 3, General Purpose Input/Output
USIC2 Channel 0 Shift Clock Output
USIC2 Channel 0 Shift Clock Input
External Bus Master Hold Request Input
Bit 10 of Port 2, General Purpose Input/Output
USIC0 Channel 1 Shift Data Output
USIC0 Channel 0 Select/Control 3 Output
CAPCOM2 CC23IO Capture Inp./ Compare Out.
External Bus Interface Address Line 23
USIC0 Channel 1 Shift Data Input
GPT12E Register CAPREL Capture Input
XC2000 Family Derivatives / Base Line
29
General Device Information
V2.0, 2009-03
XC2785X

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