SAF-XC164N-32F40F BB Infineon Technologies, SAF-XC164N-32F40F BB Datasheet - Page 15

• Manufacturer Part Number: SAF-XC164N-32F40F BB
• Description: IC MCU 16BIT FLASH 100-TQFP
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAF-XC164N-32F40F BB

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Packages: PG-TQFP-100
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 12.0 KByte
• Program Memory: 256.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: SP000277080

Table 2
Symbol Pin
P20
P20.0
P20.1
P20.4
P20.5
P20.12
Data Sheet
Num.
63
64
65
66
2
Pin Definitions and Functions (cont’d)
Input
Outp.
IO
O
O
O
I
O
Function
Port 20 is a 5-bit bidirectional I/O port. Each pin can be
programmed for input (output driver in high-impedance
state) or output. The input threshold of Port 20 is selectable
(standard or special).
The following Port 20 pins also serve for alternate functions:
RD
WR/WRL
ALE
EA
RSTOUT
Note: Port 20 pins may input configuration values (see EA).
External Memory Read Strobe, activated for
every external instruction or data read access.
External Memory Write Strobe.
In WR-mode this pin is activated for every
external data write access.
In WRL-mode this pin is activated for low byte
data write accesses on a 16-bit bus, and for
every data write access on an 8-bit bus.
Address Latch Enable Output.
Can be used for latching the address into
external memory or an address latch in the
multiplexed bus modes.
External Access Enable pin.
A low level at this pin during and after Reset
forces the XC164N to latch the configuration
from PORT0 and pin RD, and to begin
instruction execution out of external memory.
A high level forces the XC164N to latch the
configuration from pins RD, ALE, and WR, and
to begin instruction execution out of the internal
program memory. “ROMless” versions must
have this pin tied to ‘0’.
Internal Reset Indication Output.
Is activated asynchronously with an external
hardware reset. It may also be activated
(selectable) synchronously with an internal
software or watchdog reset.
Is deactivated upon the execution of the EINIT
instruction, optionally at the end of reset, or at
any time (before EINIT) via user software.
13
General Device Information
Derivatives
XC164N-32
V1.0, 2006-08