SAF-XC164N-32F40F BB Infineon Technologies, SAF-XC164N-32F40F BB Datasheet - Page 21

• Manufacturer Part Number: SAF-XC164N-32F40F BB
• Description: IC MCU 16BIT FLASH 100-TQFP
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAF-XC164N-32F40F BB

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Packages: PG-TQFP-100
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 12.0 KByte
• Program Memory: 256.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: SP000277080

bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7,
RH7) so-called General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,
any location in the DPRAM is bitaddressable.
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC166 Family. Therefore, they should
either not be accessed, or written with zeros, to ensure upward compatibility.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 12 Mbytes (approximately, see
be connected to the microcontroller.
Table 3
Address Area
Flash register space
Reserved (Acc. trap)
Reserved for PSRAM
Program SRAM
Reserved for program
memory
Program Flash/ROM
Reserved
External memory area
External IO area
Reserved
External memory area
Data RAMs and SFRs
External memory area
1) Accesses to the shaded areas generate external bus accesses.
2) The areas marked with “<” are slightly smaller than indicated, see column “Notes”.
3) Not defined register locations return a trap code.
4) Depends on the respective derivative. The derivatives are listed in
5) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
Data Sheet
peripherals properly.
XC164N Memory Map
5)
Start Loc.
FF’F000
F8’0000
E0’1800
E0’0000
C4’0000
C0’0000
BF’0000
40’0000
20’0800
20’0000
01’0000
00’8000
00’0000
H
H
H
H
H
H
H
H
H
H
H
H
H
1)
End Loc.
FF’FFFF
FF’EFFF
F7’FFFF
E0’17FF
DF’FFFF
C3’FFFF
BF’FFFF
BE’FFFF
3F’FFFF
20’07FF
1F’FFFF
00’FFFF
00’7FFF
19
Table
H
H
H
H
H
H
H
H
H
H
H
H
H
Area Size
4 Kbytes
< 0.5 Mbytes Minus Flash register
< 1.5 Mbytes Minus PSRAM
6 Kbytes
< 2 Mbytes
256 Kbytes
64 Kbytes
< 8 Mbytes
< 2 Mbytes
2 Kbytes
< 2 Mbytes
32 Kbytes
32 Kbytes
3) of external RAM and/or ROM can
Table
1.
2)
Functional Description
Notes
Flash only
space
Maximum
Minus Flash
4)
–
Minus reserved
segment
Minus 2 Kbytes
–
Minus segment 0
Partly used
–
Derivatives
XC164N-32
V1.0, 2006-08
3)
4)