SAK-TC1736-128F80HL AA Infineon Technologies, SAK-TC1736-128F80HL AA Datasheet - Page 108

• Manufacturer Part Number: SAK-TC1736-128F80HL AA
• Description: IC MCU 32BIT 1MB FLASH 144LQFP
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1736-128F80HL AA

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 70
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LFQFP
• Packages: PG-LQFP-144
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 48.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 24
• Program Memory: 1.0 MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

With rising number
of
accumulated jitter remains at a constant value. Further, a lower LMB-Bus clock
frequency
Figure 18-10
Figure 10
Note: The specified PLL jitter values are valid if the capacitive load per output pin does
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
Data Sheet
m
that is defined by the K2-factor of the PLL. Beyond this value of
D
not exceed
applications with many pins with high loads, driver strengths and toggle rates the
specified jitter values could be exceeded.
V
V
frequencies above 300 KHz.
The maximum peak-to peak noise on the pad supply votage, measured between
V
V
frequencies above 300 KHz.
m
±10.0
DDOSC3
PP
DDOSC
PP
±8.0
±7.0
±6.0
±4.0
±2.0
±1.0
±0.0
ns
= 100 mV for noise frequencies below 300 KHz and
= 100 mV for noise frequencies below 300 KHz and
f
LMB
0
D
m
K2
m
gives the jitter curves for several K2 /
Approximated Maximum Accumulated PLL Jitter for Typical LMB-
Bus Clock Frequencies
at pin 84 and
f
LMB
results in a higher absolute maximum jitter value.
at pin 85 and
= Max. jitter
= Number of consecutive f
= K2-divider of PLL
= 40 MHz (K2 = 10)
C
m
L
20
of clock cycles the maximum jitter increases linearly up to a value
= 20 pF with the maximum driver and sharp edge. In case of
f
LMB
V
V
SSOSC
= 40 MHz (K2 = 20)
f
40
SSOSC
LMB
= 80 MHz (K2 = 10)
at pin 83, is limited to a peak-to-peak voltage of
LMB
f
at pin 83, is limited to a peak-to-peak voltage of
LMB
f
periods
= 80 MHz (K2 = 6)
LMB
60
104
80
f
LMB
combinations.
100
Electrical Parameters
V
V
PP
PP
TC1736_PLL_JITT
= 40 mV for noise
= 40 mV for noise
120
m
the maximum
V1.1, 2009-08
TC1736
o
m
o