SAK-TC1197-512F180E AC Infineon Technologies, SAK-TC1197-512F180E AC Datasheet - Page 54

• Manufacturer Part Number: SAK-TC1197-512F180E AC
• Description: IC MCU 32BIT 4MB FLASH BGA416-10
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAK-TC1197-512F180E AC

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 180MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 219
• Program Memory Size: 4MB (4M x 8)
• Program Memory Type: FLASH
• Ram Size: 224K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 48x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Packages: PG-BGA-416
• Max Clock Frequency: 180.0 MHz
• Sram (incl. Cache): 224.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 48
• Program Memory: 4.0 MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.5.7.2
General Features
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Figure 13
Data Sheet
Extreme fast conversion, 21 cycles of
10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
Successive approximation conversion method
Two differential input channels with impedance control available on dedicated pins
Two differential input channels with impedance control overlaid with ADC1 inputs
Each differential input channel can also be used as single-ended input
Offset calibration support for each channel
Programmable gain of 1, 2, 4, or 8 for each channel
Free-running (Channel Timers) or triggered conversion modes
Trigger and gating control for external signals
Built-in Channel Timers for internal triggering
Channel timer request periods independently selectable for each channel
Selectable, programmable digital anti-aliasing and data reduction filter block with four
independent filter units
Interrupt
GS[H:A]
TS[H:A]
Control
Control
Clock
DMA
FADC Short Description
Block Diagram of the FADC Module with 4 Input Channels
f
f
FADC
CLC
SRx
SRx
V
FAREF
Control
V
FAGND
A/D
Channel
Trigger
Control
V
DDAF
V
SSAF
Reduction
Converter
f
Stage
FADC
50
Data
V
Unit
A/D
DDMF
Channel
V
Timers
clock (262.5 ns @
SSMF
V
DDIF
FAIN0P
FAIN0N
FAIN1P
FAIN1N
FAIN2P
FAIN2N
FAIN3P
FAIN3N
f
FADC
input
channel 0
input
channel 1
input
channel 2
input
channel 3
= 80 MHz)
MCB06065_m4
Introduction
V1.1, 2009-05
TC1197