AT90S2313-4PI Atmel, AT90S2313-4PI Datasheet - Page 22

• Manufacturer Part Number: AT90S2313-4PI
• Description: IC MCU 2K 4MHZ UART LV IT 20DIP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S2313-4PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

General Interrupt Mask
Register – GIMSK
22
AT90S2313
interrupt. Some of the Interrupt Flags can also be cleared by writing a logical “1” to the
flag bit position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared
(zero), the Interrupt Flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software.
If one or more interrupt conditions occur when the Global Interrupt Enable bit is cleared
(zero), the corresponding interrupt flag(s) will be set and remembered until the Global
Interrupt Enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag, and will only be remembered for
as long as the interrupt condition is active.
Note that the Status Register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) in the MCU general Control Register (MCUCR) defines whether the external
interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on
the pin will cause an interrupt request even if INT1 is configured as an output. The corre-
sponding interrupt of External Interrupt Request 1 is executed from program memory
address $002. See also “External Interrupts”.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU general Control Register (MCUCR) defines whether the External
Interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on
the pin will cause an interrupt request even if INT0 is configured as an output. The corre-
sponding interrupt of External Interrupt Request 0 is executed from program memory
address $001. See also “External Interrupts.”
• Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S2313 and always read as zero.
Bit
$3B ($5B)
Read/Write
Initial value
INT1
R/W
7
0
INT0
R/W
6
0
R
5
–
0
4
–
R
0
R
3
–
0
R
2
–
0
R
1
–
0
R
0839I–AVR–06/02
0
–
0
GIMSK