AT90S2313-4SI Atmel, AT90S2313-4SI Datasheet

Page 1

... I/O and Packages – 15 Programmable I/O Lines – 20-pin PDIP and SOIC • Operating Voltages – 2.7 - 6.0V (AT90S2313-4) – 4.0 - 6.0V (AT90S2313-10) • Speed Grades – MHz (AT90S2313-4) – MHz (AT90S2313-10) Pin Configuration PDIP/SOIC 8-bit Microcontroller with 2K Bytes of In-System Programmable Flash AT90S2313 Rev. 0839I– ...

Page 2

... Description The AT90S2313 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. ...

Page 3

... The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not active. Port D also serves the functions of various special features of the AT90S2313 as listed on page 56. Reset input. A low level on this pin for more than 50 ns will generate a Reset, even if the clock is not running ...

Page 4

... On-chip Oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 3. Figure 2. Oscillator Connections Note: Figure 3. External Clock Drive Configuration AT90S2313 4 MAX 1 HC BUFFER When using the MCU Oscillator as a clock for an external device buffer should be connected as indicated in the figure ...

Page 5

... Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Figure 4. The AT90S2313 AVR RISC Architecture Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table look-up func- tion ...

Page 6

... Global Interrupt Enable bit in the Status Register. All the different interrupts have a sep- arate Interrupt Vector in the Interrupt Vector table at the beginning of the program memory. The different interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. AT90S2313 6 0839I–AVR–06/02 ...

Page 7

... These registers are the address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined in Figure 7. Figure 7. X-, Y-, and Z-Registers 15 X-register 7 R27 ($1B) 15 Y-register 7 R29 ($1D) 15 Z-register 7 R31 ($1F) AT90S2313 0 Addr. R0 $00 R1 $01 R2 $02 … R13 $0D R14 $0E R15 ...

Page 8

... EEPROM Data Memory The AT90S2313 contains 128 bytes of EEPROM data memory organized as a sep- arate data space in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 39, specifying the EEPROM Address Register, the EEPROM Data Register and the EEPROM Control Register ...

Page 9

... When using register indirect addressing modes with automatic pre-decrement and post- increment, the address registers X, Y, and Z are used and decremented and incremented. The 32 general purpose working registers, 64 I/O Registers and the 128 bytes of data SRAM in the AT90S2313 are all directly accessible through all these addressing modes. AT90S2313 Data Address Space $00 ...

Page 10

... Program and Data The AT90S2313 AVR RISC microcontroller supports powerful and efficient addressing modes for access to the Program memory (Flash) and Data memory. This section Addressing Modes describes the different addressing modes supported by the AVR architecture. In the fig- ures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits ...

Page 11

... A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify the destination or source register. Figure 13. Data Indirect with Displacement Operand address is the result of the Y- or Z-register contents added to the address con- tained in 6 bits of the instruction word. Figure 14. Data Indirect Addressing Operand address is the contents of the X-, Y-, or Z-register. AT90S2313 11 ...

Page 12

... X-, Y-, or Z-register prior to incrementing. Constant Addressing Using Figure 17. Code Memory Constant Addressing the LPM Instruction Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 1K), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1). AT90S2313 12 0839I–AVR–06/02 ...

Page 13

... RJMP and RCALL 0839I–AVR–06/02 Figure 18. Indirect Program Memory Addressing Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register). Figure 19. Relative Program Memory Addressing Program execution continues at address The relative address k is -2048 to 2047. AT90S2313 13 ...

Page 14

... ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 21. Single-cycle ALU Operation The internal data SRAM access is performed in two System Clock cycles as described in Figure 22. AT90S2313 14 T1 System Clock Ø 1st Instruction Fetch 1st Instruction Execute ...

Page 15

... I/O Memory 0839I–AVR–06/02 Figure 22. On-chip Data SRAM Access Cycles T1 System Clock Ø Address Prev. Address Data WR Data RD The I/O space definition of the AT90S2313 is shown in Table 1. (1) Table 1. AT90S2313 I/O Space Address Hex Name Function $3F ($5F) SREG Status Register $3D ($5D) SPL ...

Page 16

... Table 1. AT90S2313 I/O Space Note: All AT90S2313 I/O and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general pur- pose working registers and the I/O space. I/O Registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions ...

Page 17

... Note that the Status Register is not automatically stored when entering an interrupt rou- tine and restored when returning from an interrupt routine. This must be handled by software. An 8-bit register at I/O address $3D ($5D) forms the Stack Pointer of the AT90S2313. 8 bits are used to address the 128 bytes of SRAM in locations $60 - $DF. Bit ...

Page 18

... Reset and Interrupt The AT90S2313 provides 10 different interrupt sources. These interrupts and the sepa- rate Reset Vector each have a separate Program Vector in the program memory space. Handling All the interrupts are assigned individual enable bits that must be set (one) together with the I-bit in the Status Register in order to enable the interrupt ...

Page 19

... Reset Sources 0839I–AVR–06/02 The AT90S2313 has three sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ). POT • External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns. • ...

Page 20

... By holding the RESET pin low for a period after V been applied, the Power-on Reset period can be extended. Refer to Figure 25 for a tim- ing example of this. Figure 24. MCU Start-up, RESET Tied to V INTERNAL Figure 25. MCU Start-up, RESET Controlled Externally AT90S2313 20 FSTRT Time-out at V Programmed 0.28 ms Unprogrammed 16 ...

Page 21

... TOUT Figure 27. Watchdog Reset during Operation The AT90S2313 has two 8-bit Interrupt Mask Control Registers: the GIMSK (General Interrupt Mask Register) and the TIMSK (Timer/Counter Interrupt Mask Register). When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter- rupts are disabled ...

Page 22

... INT0 is configured as an output. The corre- sponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 – Res: Reserved Bits These bits are reserved bits in the AT90S2313 and always read as zero. AT90S2313 22 Bit ...

Page 23

... The flag is always cleared when INT0 is configured as level interrupt. • Bits 5..0 – Res: Reserved Bits These bits are reserved bits in the AT90S2313 and always read as zero. Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is active. ...

Page 24

... ICF1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]). • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the AT90S2313 and always reads as zero. • Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow Interrupt is enabled ...

Page 25

... MCUCR 0839I–AVR–06/02 • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the AT90S2313 and always reads as zero. • Bit 1 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical “ ...

Page 26

... Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate an interrupt request as long as the pin is held low. AT90S2313 26 ISC11 ISC10 Description ...

Page 27

... Time-out period t wise, the device will not wake up. The AT90S2313 provides two general purpose Timer/Counters – one 8-bit T/C and one 16-bit T/C. The Timer/Counters have individual prescaling selection from the same 10- bit prescaling timer ...

Page 28

... The 8-bit Timer/Counter0 features both a high-resolution and a high-accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make the Timer/Counter0 useful for lower speed functions or exact timing functions with infre- quent actions. Figure 29. Timer/Counter0 Block Diagram AT90S2313 28 T0 0839I–AVR–06/02 ...

Page 29

... Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90S2313 and always read zero. • Bits 2,1,0 – CS02, CS01, CS00: Clock Select0, Bit 2,1 and 0 The Clock Select0 bits 2, 1, and 0 define the prescaling source of Timer/Counter0. ...

Page 30

... The Timer/Counter1 supports an Output Compare function using the Output Compare Register 1A (OCR1A) as the data source to be compared to the Timer/Counter1 con- tents. The Output Compare functions include optional clearing of the counter on compare matches, and actions on the Output Compare pin 1 on compare matches. AT90S2313 30 T1 0839I–AVR–06/02 ...

Page 31

... Set the OC1 output line (to one). Notes PWM mode, these bits have a different function. Refer to Table 12 for a detailed description. 2. The initial state of the OC1 output line is undefined. • Bits 5..2 – Res: Reserved Bits These bits are reserved bits in the AT90S2313 and always read zero. AT90S2313 – ...

Page 32

... Register (ICR1) on the rising edge of the input capture pin (ICP). • Bits 5, 4 – Res: Reserved Bits These bits are reserved bits in the AT90S2313 and always read zero. • Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match ...

Page 33

... CPU and the data of the high byte TCNT1H is placed in the TEMP Register. When the CPU reads the data in the high byte TCNT1H, the CPU receives the data in the TEMP Register. Consequently, the low byte TCNT1L must be accessed first for a full 16-bit register read operation. AT90S2313 Description Stop, the Timer/Counter1 is stopped. CK ...

Page 34

... CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP Register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP Register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. AT90S2313 34 Bit 15 ...

Page 35

... They are latched when Timer/Counter1 reaches TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A write. See Figure 32 for an example. Figure 32. Effects on Unsynchronized OCR1 Latching Compare Value changes Compare Value changes AT90S2313 Timer TOP Value Frequency $00FF (255) f TC1 ...

Page 36

... TOV1 is set, provided that Timer Overflow Interrupt1 and global interrupts are enabled). This also applies to the Timer Output Compare1 Flag and interrupt. AT90S2313 36 If the Compare Register contains the TOP value and the prescaler is not in use (CS12..CS10 = 001), the PWM output will not produce any pulse at all, because the up- counting and down-counting values are reached simultaneously ...

Page 37

... Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the AT90S2313 and will always read as zero. • Bit 4 – WDTOE: Watchdog Turn-off Enable This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will not be disabled ...

Page 38

... The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in Table 14. Table 14. Watchdog Timer Prescale Select Note: AT90S2313 38 be written to WDE even though it is set to 1 before the disable operation starts. Watchdog. Number of ...

Page 39

... Bit 7 – Res: Reserved Bit This bit is a reserved bit in the AT90S2313 and will always read as zero. • Bit 6..0 – EEAR6..0: EEPROM Address The EEPROM Address Register (EEAR6..0) specifies the EEPROM address in the 128 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 127 ...

Page 40

... EEPROM Control Register – EECR • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90S2313 and will always read as zero. • Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written ...

Page 41

... CPU from attempting to decode and execute instructions, effec- tively protecting the EEPROM Registers from unintentional writes. 3. Store constants in Flash memory if the ability to change memory contents from software is not required. Flash memory cannot be updated by the CPU and will not be subject to corruption. AT90S2313 Reset Protection circuit, often CC . This CC ...

Page 42

... UART The AT90S2313 features a full duplex (separate Receive and Transmit Registers) Uni- versal Asynchronous Receiver and Transmitter (UART). The main features are: • • • • • • • • Data Transmission A block schematic of the UART transmitter is shown in Figure 34. Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Register (UDR). Data is transferred from UDR to the Transmit Shift Register when: • ...

Page 43

... Let sample 1 denote the first zero-sample. Following the 1-to-0 transition, the receiver samples the RXD pin at samples 8, 9 and 10. If two or more of these three samples are AT90S2313 43 ...

Page 44

... The ninth data bit to be transmitted is the TXB8 bit in UCR Register. This bit must be set to the wanted value before a transmission is initi- ated by writing to the UDR Register. The ninth data bit received is the RXB8 bit in the UCR Register. AT90S2313 44 0839I–AVR–06/02 ...

Page 45

... UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven data transmittal is used, the UART Data Register Empty Interrupt routine must write UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt routine terminates. UDRE is set (one) during reset to indicate that the transmitter is ready. AT90S2313 ...

Page 46

... The OR bit is cleared (zero) when data is received and transferred to UDR. • Bits 2..0 – Res: Reserved Bits These bits are reserved bits in the AT90S2313 and will always read as zero. UART Control Register – UCR • Bit 7 – RXCIE: RX Complete Interrupt Enable When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Com- plete Interrupt routine to be executed provided that global interrupts are enabled ...

Page 47

... UBRR= 19200 UBRR= 0.0 UBRR= 23 28800 UBRR= 0.0 UBRR= 15 38400 UBRR= 11 0.0 UBRR= 57600 UBRR= 0.0 UBRR= 7 76800 UBRR= 5 0.0 UBRR= 115200 UBRR= 3 0.0 UBRR= AT90S2313 ------------------------------------ - 16(UBRR + 1) 2 MHz %Error 2.4576 MHz %Error 47 0.0 UBRR= 51 0.2 UBRR= 23 0.0 UBRR= 25 0.2 UBRR= 11 ...

Page 48

... Idle modes. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. • Bit 6 – Res: Reserved Bit This bit is a reserved bit in the AT90S2313 and will always read as zero. AT90S2313 48 Bit ...

Page 49

... Comparator Interrupt on Falling Output Edge 1 1 Comparator Interrupt on Rising Output Edge Note: 1. When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis- abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. AT90S2313 49 ...

Page 50

... When the pins are used for the alternate function, the DDRB and PORTB Registers have to be set according to the alternate function description. Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB AT90S2313 50 Port Pin Alternate Functions PB0 AIN0 (Analog Comparator positive input) PB1 ...

Page 51

... AIN0 – Port B, Bit 0 AIN0, Analog Comparator Positive Input. When configured as an input (DDB0 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB0 is cleared [zero]), this pin also serves as the positive input of the On-chip Analog Comparator. AT90S2313 (1) Pull-up Comment ...

Page 52

... Port B Schematics Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 38. Port B Schematic Diagram (Pins PB0 and PB1) AT90S2313 52 0839I–AVR–06/02 ...

Page 53

... Figure 39. Port B Schematic Diagram (Pin PB3) MOS PULL- UP PB3 WP: WRITE PORTB WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB Figure 40. Port B Schematic Diagram (Pins PB2 and PB4) AT90S2313 RD RESET DDB3 C WD RESET PORTB3 COM1A0 COM1A1 OUTPUT COMP ...

Page 54

... Figure 41. Port B Schematic Diagram (Pin PB5) Figure 42. Port B Schematic Diagram (Pin PB6) AT90S2313 54 0839I–AVR–06/02 ...

Page 55

... PD3 INT1 (External interrupt 1 input) PD4 TO (Timer/Counter0 external input) PD5 T1 (Timer/Counter1 external input) PD6 ICP (Timer/Counter1Input Capture pin) When the pins are used for the alternate function, the DDRD and PORTD Registers have to be set according to the alternate function description. AT90S2313 55 ...

Page 56

... Timer/Counter1 Input Capture pin. See the Timer/Counter1 description for further details. • T1 – Port D, Bit 5 T1, Timer 1 Clock source. See the Timer description for further details. • T0 – Port D, Bit 4 T0, Timer/Counter0 Clock source. See the Timer description for further details. AT90S2313 56 Bit $12 ($32) – ...

Page 57

... Figure 44. Port D Schematic Diagram (Pin PD0) MOS PULL- UP PD0 WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD RXD: UART RECEIVE DATA RXEN: UART RECEIVE ENABLE AT90S2313 RD RESET Q D DDD0 C WD RESET Q D PORTD0 RXEN RXD 57 ...

Page 58

... Figure 45. Port D Schematic Diagram (Pin PD1) Figure 46. Port D Schematic Diagram (Pins PD2 and PD3) AT90S2313 58 MOS PULL- UP PD1 WRITE PORTD WP: WD: WRITE DDRD RL: READ PORTD LATCH READ PORTD PIN RP: RD: READ DDRD TXD: UART TRANSMIT DATA UART TRANSMIT ENABLE TXEN: RD RESET ...

Page 59

... Figure 47. Port D Schematic Diagram (Pins PD4 and PD5) MOS PULL- UP PDn WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD Figure 48. Port D Schematic Diagram (Pin PD6) AT90S2313 RD RESET DDDn C WD RESET PORTDn TIMERm CLOCK SENSE CONTROL SOURCE MUX ...

Page 60

... Memory Programming Program and Data The AT90S2313 MCU provides two Lock bits that can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 21. The Lock bits Memory Lock Bits can only be erased with the Chip Erase operation. ...

Page 61

... This section describes how to parallel program and verify Flash Program memory, EEPROM data memory, Lock bits and Fuse bits in the AT90S2313. In this section, some pins of the AT90S2313 are referenced by signal names describing their function during parallel programming. Pins not described in the following table are referenced by pin names ...

Page 62

... Load Command “Chip Erase” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS to “0”. 3. Set DATA to “1000 0000”. This is the command for Chip Erase. 4. Give XTAL1 a positive pulse. This loads the command. AT90S2313 62 Signal Name in Programming Mode Pin Name ...

Page 63

... Give XTAL1 a positive pulse. This loads the data high byte. G: Write Data High Byte 1. Set BS to “1”. This selects high data. 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3. Wait until RDY/BSY goes high to program the next byte. (See Figure 51 for signal waveforms.) AT90S2313 63 ...

Page 64

... These considerations also apply to EEPROM programming and Flash, EEPROM and signature byte reading. Figure 50. Programming the Flash Figure 51. Programming the Flash (Continued) AT90S2313 64 The command needs only be loaded once when writing or reading multiple memory locations. Address high byte needs only be loaded before programming a new 256-word page in the Flash. Skip writing the data value $FF ...

Page 65

... D: Load Data Low Byte. Bit n = “0” programs the Lock bit. Bit 2 = Lock Bit2 Bit 1 = Lock Bit1 Bit “1”. These bits are reserved and should be left unprogrammed (“1”). 3. E: Write Data Low Byte. The Lock bits can only be cleared by executing Chip Erase. AT90S2313 is t WLWH_PFB 65 ...

Page 66

... The algorithm for reading the signature bytes is as follows (refer to “Programming the Flash” on page 63 for details on command and address loading Load Command “0000 1000” Load Address Low Byte ($00 - $02). 3. Set OE to “1”. AT90S2313 66 read at DATA (“0” means programmed). Bit 7 = Lock Bit1 Bit 6 = Lock Bit2 ...

Page 67

... OE High to DATA Tri-stated OHDZ t WR Pulse Width Low for Chip Erase WLWH_CE WR Pulse Width Low for Programming the Fuse t Bits WLWH_PFB Notes: 1. Use t for chip erase and t WLWH_CE held longer than t WLWH AT90S2313 t XLWL t t XLDX BVWL t WLWH t WHRL t XLOL t OLDV = 25 C ± 10%, V ...

Page 68

... Low: > 2 XTAL1 clock cycle High: > 2 XTAL1 clock cycles Serial Programming When writing serial data to the AT90S2313, data is clocked on the rising edge of SCK. Algorithm When reading data from the AT90S2313, data is clocked on the falling edge of SCK. See Figure 54, Figure and Table 29 for timing details. ...

Page 69

... This does not apply if the EEPROM is reprogrammed without first chip-erasing the device. Table 27. Read Back Value during EEPROM Polling Part AT90S2313 AT90S2313 before transmitting the next instruction. WD_PROG before programming the next byte. See Table P1 ...

Page 70

... – Low byte, 1 – High Byte data out data in don’t care Lock bit Lock bit 2. Note: 1. The signature bytes are not readable in lock mode 3, i.e. both Lock bits programmed. AT90S2313 70 WD_PROG Instruction Format Byte 2 ...

Page 71

... SHOX t SCK Low to MISO Valid SLIV Table 30. Minimum Wait Delay after the Chip Erase Instruction Symbol 3. WD_ERASE Table 31. Minimum Wait Delay after Writing a Flash or EEPROM Location Symbol 3. WD_PROG AT90S2313 t t SLSH SHOX t SHSL t SLIV = - Min Typ = 2.7 - 6.0V) 0 250.0 = 4.0 - 6.0V) 0 100 ...

Page 72

... I/O Pin Pull-up Resistor I/O I Power Supply Current CC (5) I Power-down Mode CC Analog Comparator V ACIO Input Offset Voltage Analog Comparator I ACLK Input Leakage Current Analog Comparator t ACPD Propagation Delay AT90S2313 72 *NOTICE: +0.5V CC Condition (Except XTAL1) (XTAL1) (Except XTAL1, RESET) 0.6 V (XTAL1) 0.7 V (RESET mA, V ...

Page 73

... Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL AT90S2313 may exceed the related specification. Pins are OL may exceed the related specification. Pins are 2. 4. Min Max Min 250.0 100 ...

Page 74

... The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the dif- ferential current drawn by the Watchdog Timer. Figure 57. Active Supply Current vs. Frequency AT90S2313 74 • V • f where C = load capacitance, V ...

Page 75

... Figure 58. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs 2.5 3 3.5 Figure 59. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY AT90S2313 CC cc FREQUENCY = 4 MHz ˚ 4.5 5 5 25˚ Frequency (MHz ˚ ...

Page 76

... Figure 60. Idle Supply Current vs. V Figure 61. Power-down Supply Current vs. V AT90S2313 76 CC IDLE SUPPLY CURRENT vs. V FREQUENCY = 4 MHz 3.5 3 2.5 2 1 2.5 3 3.5 POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0 2.5 3 3.5 ...

Page 77

... Figure 62. Power-down Supply Current vs. V POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 160 140 120 100 2.5 3 3.5 Figure 63. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs. V 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 2.5 3 AT90S2313 4.5 5 5 ˚ 3.5 4 4.5 5 5 ˚ ˚ ...

Page 78

... Note: Figure 64. Analog Comparator Offset Voltage vs. Common Mode Voltage Figure 65. Analog Comparator Offset Voltage vs. Common Mode Voltage AT90S2313 78 Analog Comparator offset voltage is measured as absolute offset. ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE 0.5 1 1.5 2 Common Mode Voltage (V) ANALOG COMPARATOR OFFSET VOLTAGE vs. ...

Page 79

... Figure 66. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT -10 0 0.5 1 1.5 2 2.5 Figure 67. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 1400 1200 1000 800 600 400 200 0 2 2.5 3 3.5 AT90S2313 ˚ 3.5 4 4.5 5 5.5 6 6 ˚ 4.5 5 5.5 V (V) cc ...

Page 80

... Note: Figure 68. Pull-up Resistor Current vs. Input Voltage Figure 69. Pull-up Resistor Current vs. Input Voltage AT90S2313 80 Sink and source capabilities of I/O ports are measured on one pin at a time. PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 120 ˚ A 100 ˚ 0.5 1 1.5 2 PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ...

Page 81

... Figure 70. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 1 Figure 71. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ˚ ˚ 0.5 1 1.5 AT90S2313 ˚ ˚ A 1.5 2 2 2.5 3 3.5 4 4 ...

Page 82

... Figure 72. I/O Pin Sink Current vs. Output Voltage Figure 73. I/O Pin Source Current vs. Output Voltage AT90S2313 82 I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 V I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ˚ ˚ 0 ˚ ˚ 1 2.5 3 (V) OH 0839I–AVR–06/02 ...

Page 83

... Figure 74. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V 2.5 2 1.5 1 0.5 0 2.7 Figure 75. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 AT90S2313 ˚ A 4.0 5 ˚ A 4.0 5 ...

Page 84

... Some of the Status Flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a “1” back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. AT90S2313 84 Bit 6 ...

Page 85

... Branch if Half-carry Flag Cleared BRTS k Branch if T-Flag Set BRTC k Branch if T-Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled 0839I–AVR–06/02 AT90S2313 Operation Flags Z,C,N,V Z,C,N,V,H Rdh:Rdl Rdh:Rdl + K Z,C,N,V Z,C,N,V Z,C,N,V,H ...

Page 86

... CLV Clear Two’s Complement Overflow SET Set T in SREG CLT Clear T in SREG SEH Set Half-carry Flag in SREG CLH Clear Half-carry Flag in SREG NOP No Operation SLEEP Sleep WDR Watchdog Reset AT90S2313 86 Operation Flags Rd Rr None Rd K None Rd (X) None Rd (X None ...

Page 87

... Wide, Plastic Dual Inline Package (PDIP) 20S 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 0839I–AVR–06/02 Ordering Code Package AT90S2313-4PC 20P3 AT90S2313-4SC 20S AT90S2313-4PI 20P3 AT90S2313-4SI 20S AT90S2313-10PC 20P3 AT90S2313-10SC 20S AT90S2313-10PI 20P3 AT90S2313-10SI 20S Package Type AT90S2313 ...

Page 88

... Packaging Information 20P3 A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT90S2313 88 D PIN SYMBOL TITLE 20P3, 20-lead (0.300" ...

Page 89

... PIN 1 ID PIN 1 1.27 (0.050) BSC 13.00 (0.5118) 12.60 (0.4961) 0.30(0.0118) 0.10 (0.0040) 0º ~ 8º 1.27 (0.050) 0.40 (0.016) *Controlling dimension: Inches AT90S2313 10.65 (0.419) 7.60 (0.2992) 10.00 (0.394) 7.40 (0.2914) 2.65 (0.1043) 2.35 (0.0926) 0.32 (0.0125) 0.23 (0.0091) 89 ...

Page 90

... Watchdog Timer.................................................................................. 37 EEPROM Read/Write Access............................................................. 39 Prevent EEPROM Corruption ............................................................................. 41 UART.................................................................................................... 42 Data Transmission.............................................................................................. 42 Data Reception ................................................................................................... 43 UART Control ..................................................................................................... 45 Analog Comparator ............................................................................ 48 I/O Ports............................................................................................... 50 Port B.................................................................................................................. 50 Port D.................................................................................................................. 55 Memory Programming........................................................................ 60 Program and Data Memory Lock Bits................................................................. 60 Fuse Bits............................................................................................................. 60 Signature Bytes .................................................................................................. 60 Programming the Flash and EEPROM............................................................... 60 AT90S2313 i ...

Page 91

... Electrical Characteristics................................................................... 72 Typical Characteristics ...................................................................... 74 Register Summary .............................................................................. 84 Instruction Set Summary ................................................................... 85 Ordering Information.......................................................................... 87 Packaging Information ....................................................................... 88 Table of Contents .................................................................................. i AT90S2313 ii Parallel Programming ......................................................................................... 61 Parallel Programming Characteristics ................................................................ 67 Serial Downloading ............................................................................................. 68 Serial Programming Characteristics ................................................................... 71 Absolute Maximum Ratings*............................................................................... 72 DC Characteristics.............................................................................................. 72 External Clock Drive Waveforms ........................................................................ 73 External Clock Drive ........................................................................................... 73 20P3 ................................................................................................................... 88 20S ..................................................................................................................... 89 0839I–AVR–06/02 ...

Page 92

... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...