AT90S4433-8PC Atmel, AT90S4433-8PC Datasheet - Page 63
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AT90S4433-8PC
Manufacturer Part Number
AT90S4433-8PC
Description
IC MCU 4K FLSH 8MHZ A/D 28DIP
Manufacturer
Atmel
Series
AVR® 90Sr
Datasheet
1.AT90S4433-8AC.pdf
(126 pages)
Specifications of AT90S4433-8PC
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90S4433-8PC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
1042H–AVR–04/03
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined
by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit
is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when execut-
ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a
logical “1” to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Ana-
log Comparator interrupt is activated. When cleared (zero), the interrupt is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When set (one), this bit enables the Input Capture function in Timer/Counter1 to be trig-
gered by the Analog Comparator. The comparator output is, in this case, directly
connected to the Input Capture front-end logic, making the comparator utilize the noise
canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When
cleared (zero), no connection between the Analog Comparator and the Input Capture
function is given. To make the comparator trigger the Timer/Counter1 Input Capture
interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one).
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events trigger the Analog Comparator interrupt.
The different settings are shown in Table 20.
Table 20. ACIS1/ACIS0 Settings
Note:
Caution: Using the SBI or CBI instruction on bits other than ACI in this register will write
a one back into ACI if it is read as set, thus clearing the flag.
ACIS1
0
0
1
1
1. When changing the ACIS1/ACIS0 bits, the Analog Comparator interrupt must be dis-
abled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise, an
interrupt can occur when the bits are changed.
ACIS0
0
1
0
1
Interrupt Mode
Comparator Interrupt on Output Toggle.
Reserved
Comparator Interrupt on Falling Output Edge.
Comparator Interrupt on Rising Output Edge.
(1)
AT90S/LS4433
63