AT90S8535-8JC Atmel, AT90S8535-8JC Datasheet - Page 55
![IC MCU 8K FLSH 8MHZ A/D 44PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
AT90S8535-8JC
Manufacturer Part Number
AT90S8535-8JC
Description
IC MCU 8K FLSH 8MHZ A/D 44PLCC
Manufacturer
Atmel
Series
AVR® 90Sr
Specifications of AT90S8535-8JC
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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1041H–11/01
Figure 38. SPI Master-slave Interconnection
The system is single-buffered in the transmit direction and double-buffered in the
receive direction. This means that bytes to be transmitted cannot be written to the SPI
Data Register before the entire shift cycle is completed. When receiving data, however,
a received byte must be read from the SPI Data Register before the next byte has been
completely shifted in. Otherwise, the first byte is lost.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK and SS pins is
overridden according to Table 22.
Table 22. SPI Pin Overrides
Note:
MOSI
MISO
SCK
Pin
SS
See “Alternate Functions of Port B” on page 79 f
define the direction of the user-defined SPI pins.
CLOCK GENERATOR
MSB
8 BIT SHIFT REGISTER
Direction, Master SPI
User Defined
Input
User Defined
User Defined
SPI
MASTER
LSB
V
MISO
MOSI
SCK
SS
CC
MISO
MOSI
SCK
SS
Direction, Slave SPI
Input
User Defined
Input
Input
MSB
8 BIT SHIFT REGISTER
or a detailed description of how to
AT90S/LS8535
MASTER
LSB
55
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