AT90S8535-8JC Atmel, AT90S8535-8JC Datasheet - Page 57
AT90S8535-8JC
Manufacturer Part Number
AT90S8535-8JC
Description
IC MCU 8K FLSH 8MHZ A/D 44PLCC
Manufacturer
Atmel
Series
AVR® 90Sr
Specifications of AT90S8535-8JC
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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SPI Control Register – SPCR
1041H–11/01
Figure 40. SPI Transfer Format with CPHA = 1 and DORD = 0
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set
and the global interrupts are enabled.
• Bit 6 – SPE: SPI Enable
When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI
operations.
• Bit 5 – DORD: Data Order
When the DORD bit is set (one), the LSB of the data word is transmitted first.
When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI Mode when set (one) and Slave SPI Mode when cleared
(zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be
cleared and SPIF in SPSR will become set. The user will then have to set MSTR to re-
enable SPI Master Mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is
low when idle. Refer to Figure 39. and Figure 40. for additional information.
• Bit 2 – CPHA: Clock Phase
Refer to Figure 40 or Figure 41 for the functionality of this bit.
Bit
$0D ($2D)
Read/Write
Initial Value
SPIE
R/W
7
0
SPE
R/W
6
0
DORD
R/W
5
0
MSTR
R/W
4
0
CPOL
R/W
3
0
CPHA
R/W
2
0
AT90S/LS8535
SPR1
R/W
1
0
SPR0
R/W
0
0
SPCR
57
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