PIC16LF84AT-04/SO Microchip Technology, PIC16LF84AT-04/SO Datasheet - Page 48
![IC MCU FLASH 1KX14 EE 18SOIC](/photos/6/76/67656/150-18-soic_sml.jpg)
PIC16LF84AT-04/SO
Manufacturer Part Number
PIC16LF84AT-04/SO
Description
IC MCU FLASH 1KX14 EE 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F84A-04P.pdf
(88 pages)
2.PIC16F84A-04P.pdf
(6 pages)
3.PIC16LF84A-04P.pdf
(125 pages)
4.PIC16LF84A-04P.pdf
(4 pages)
Specifications of PIC16LF84AT-04/SO
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
18-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Connectivity
-
PIC16F8X
8.9
The PIC16F8X has 4 sources of interrupt:
• External interrupt RB0/INT pin
• TMR0 overflow interrupt
• PORTB change interrupts (pins RB7:RB4)
• Data EEPROM write complete interrupt
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also contains
the individual and global interrupt enable bits.
The global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. Bit GIE is cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
interrupt routine as well as sets the GIE bit, which
re-enable interrupts.
FIGURE 8-16: INTERRUPT LOGIC
DS30430C-page 48
Interrupts
INTE
RBIF
RBIE
EEIE
INTF
EEIF
T0IE
T0IF
GIE
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
When an interrupt is responded to; the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. For external interrupt events, such as the
RB0/INT pin or PORTB change interrupt, the interrupt
latency will be three to four instruction cycles. The
exact latency depends when the interrupt event occurs
(Figure 8-17). The latency is the same for both one and
two cycle instructions. Once in the interrupt service
routine the source(s) of the interrupt can be determined
by polling the interrupt flag bits. The interrupt flag bit(s)
must be cleared in software before re-enabling
interrupts to avoid infinite interrupt requests.
Note 1: Individual interrupt flag bits are set
Wake-up
(If in SLEEP mode)
Interrupt to CPU
regardless
corresponding mask bit or the GIE bit.
of
1998 Microchip Technology Inc.
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