ATTINY15L-1PI Atmel, ATTINY15L-1PI Datasheet - Page 21

• Manufacturer Part Number: ATTINY15L-1PI
• Description: IC AVR MCU 1K FLASH 2.7V 8DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY15L-1PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 1.6MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (512 x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Ram Size: -
• Connectivity: -

The Timer/Counter Interrupt
Flag Register – TIFR
1187H–AVR–09/07
vector $003) is executed if a compare match A in Timer/Counter1 occurs, i.e., when the
OCF1A bit is set (one) in the Timer/Counter Interrupt Flag Register (TIFR).
• Bit 5..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny15L and always read as zero.
• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector
$004) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set
(one) in the Timer/Counter Interrupt Flag Register (TIFR).
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector
$005) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set
(one) in the Timer/Counter Interrupt Flag Register (TIFR).
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
• Bit 6 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and
the data value in OCR1A (Output Compare Register 1A). OCF1A is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, OCF1A
is cleared by writing a logical “1” to the flag. When the I-bit in SREG, OCIE1A, and
OCF1A are set (one), the Timer/Counter1 compare match A interrupt is executed.
• Bits 5..3 – Res: Reserved bits
These bits are reserved bits in the ATtiny15L and always read as zero.
• Bit 2 – TOV1: Timer/Counter1 Overflow Flag
The bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV1 is cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE1
(Tim er/Co un ter1 Ove rflow Inte rrup t En able) an d TO V1 a re set (o ne) , th e
Timer/Counter1 Overflow Interrupt is executed.
Bit
$38
Read/Write
Initial Value
R
7
–
0
OCF1A
R/W
6
0
R
5
–
0
R
4
–
0
R
3
–
0
TOV1
R/W
2
0
TOV0
R/W
1
0
ATtiny15L
R
0
–
0
TIFR
21