ATMEGA163-8AI Atmel, ATMEGA163-8AI Datasheet - Page 138

• Manufacturer Part Number: ATMEGA163-8AI
• Description: IC AVR MCU 16K A/D 8MHZ 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA163-8AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Setting the Boot Loader Lock
Bits by SPM
Reading the Fuse and Lock
Bits from Software
138
ATmega163(L)
Table 53. Boot Lock Bit0 Protection Modes (Application Section)
Note:
Table 54. Boot Lock Bit1 Protection Modes (Boot Loader Section)
Note:
To set the Boot Loader Lock bits, write the desired data to R0, write “00001001” to
SPMCR and execute SPM within four clock cycles after writing SPMCR. The only
accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot
Loader section from any software update by the MCU.
If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed
if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in
SPMCR.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits,
load the Z-pointer with $0001 and set the BLBSET and SPMEN bits in SPMCR. When
an LPM instruction is executed within five CPU cycles after the BLBSET and SPMEN
bits are set in SPMCR, the value of the Lock bits will be loaded in the destination regis-
ter. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lock
bits or if no SPM, or LPM, instruction is executed within four, respectively five, CPU
cycles. When BLBSET and SPMEN are cleared, LPM will work as described in “Con-
stant Addressing Using The LPM and SPM Instructions” on page 15 and in the
Instruction set Manual.
Bit
R0
BLB0 mode
BLB1 mode
1
2
3
4
1
2
3
4
1. “1” means unprogrammed, “0” means programmed
1. “1” means unprogrammed, “0” means programmed
BLB02
BLB12
7
1
1
1
0
0
1
1
0
0
6
1
BLB01
BLB11
1
0
0
1
1
0
0
1
BLB12
5
Protection
No restrictions for SPM, LPM accessing the Application
section
SPM is not allowed to write to the Application section
SPM is not allowed to write to the Application section, and
LPM executing from the Boot Loader section is not
allowed to read from the Application section
LPM executing from the Boot Loader section is not
allowed to read from the Application section
Protection
No restrictions for SPM, LPM accessing the Boot Loader
section
SPM is not allowed to write to the Boot Loader section
SPM is not allowed to write to the Boot Loader section,
and LPM executing from the Application section is not
allowed to read from the Boot Loader section. If code is
executed from Boot section, the interrupts are disabled
when BLB12 is programmed.
LPM executing from the Application section is not allowed
to read from the Boot Loader section. If code is executed
from Boot section, the interrupts are disabled when BLB12
is programmed.
BLB11
4
BLB02
3
BLB01
2
(1)
1
1
(1)
1142E–AVR–02/03
0
1