ATMEGA163-8AI Atmel, ATMEGA163-8AI Datasheet - Page 20

• Manufacturer Part Number: ATMEGA163-8AI
• Description: IC AVR MCU 16K A/D 8MHZ 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA163-8AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The Status Register – SREG
20
ATmega163(L)
The AVR Status Register – SREG – at I/O space location $3F ($5F) is defined as:
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in the Interrupt Mask Registers. If
the Global Interrupt Enable Register is cleared (zero), none of the interrupts are enabled
independent of the values of the Interrupt Mask Registers. The I-bit is cleared by hard-
ware after an interrupt has occurred, and is set by the RETI instruction to enable
subsequent interrupts.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the Register File can be cop-
ied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a half carry in some arithmetic operations. See the
Instruction Set Description for detailed information.
• Bit 4 – S: Sign Bit, S = N
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Comple-
ment Overflow Flag V. See the Instruction Set Description for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See
the Instruction Set Description for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See
the Instruction Set Description for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the
Instruction Set Description for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction
Set Description for detailed information.
Note that the Status Register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
Bit
$3F ($5F)
Read/Write
Initial Value
R/W
7
0
I
R/W
6
T
0
V
R/W
H
5
0
R/W
S
4
0
R/W
V
3
0
R/W
N
2
0
R/W
1
Z
0
R/W
1142E–AVR–02/03
C
0
0
SREG