AT91M42800-33CI Atmel, AT91M42800-33CI Datasheet - Page 11

• Manufacturer Part Number: AT91M42800-33CI
• Description: IC ARM7 MCU 144 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M42800-33CI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: WDT
• Number Of I /o: 54
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• For Use With: AT91EB42 - KIT EVAL FOR ARM AT91M42800A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: AT91M4280033CI

Product Overview
Power Supply
The AT91M42800 has three kinds of power supply pins:
• VDDCORE pins, which power the chip core
• VDDIO pins, which power the I/O lines
• VDDPLL pins, which power the oscillator and PLL cells
VDDCORE and VDDIO allow core power consumption to
be reduced by supplying it with a lower voltage than the I/O
lines. The VDDCORE pins must never be powered at a
voltage greater than the supply voltage applied to the
VDDIO.
The VDDPLL pin is used to supply the oscillator and both
PLLs. The voltage applied on these pins is typically 3.3V,
and it must not be lower than VDDCORE.
Typical supported voltage combinations are shown in the
following table:
Input/Output Considerations
After the reset, the peripheral I/Os are initialized as inputs
to provide the user with maximum flexibility. It is recom-
mended that in any application phase, the inputs to the
AT91M42800 Microcontroller be held at valid logic levels to
minimize the power consumption.
Clock Generator
The AT91M42800 Microcontroller embeds a 32.768 kHz
oscillator that generates the Slow Clock (SLCK).
The AT91M42800 Microcontroller has a fully static design
and works either on the Master Clock (MCK), generated
from the Slow Clock by means of the two integrated PLLs,
or on the Slow Clock (SLCK).
These clocks are also provided as an output of the device
on the pin MCKO, which is multiplexed with a general-pur-
pose I/O line. While NRST is active, and after the reset, the
MCKO is valid and outputs an image of the SLCK signal.
The PIO Controller must be programmed to use this pin as
standard I/O line.
Pins
VDDCORE
VDDIO
VDDPLL
Max Freq
33 MHz
3.3V
5.0V
3.3V
Nominal Supply Voltages
3.0V or 3.3V
3.0V or 3.3V
3.0V or 3.3V
33 MHz
17 MHz
2.0V
3.3V
3.3V
Reset
Reset initializes the user interface registers to their default
states as defined in the peripheral sections of this
datasheet and forces the ARM7TDMI to perform the next
instruction fetch from address zero. Except for the program
counter the ARM core registers do not have defined reset
states. When reset is active, the inputs of the AT91M42800
must be held at valid logic levels. The EBI address lines
drive low during reset. All the peripheral clocks are disabled
during reset to save power.
NRST Pin
NRST is the active low reset input. It is asserted asynchro-
nously, but exit from reset is synchronized internally to the
slow clock (SLCK). At power-up, NRST must be active until
the on-chip oscillator is stable. During normal operation,
NRST must be active for a minimum of 10 oscillator clock
cycles to ensure correct initialization.
The pins BMS and NTRI are sampled during the 10 clock
cycles just prior to the rising edge of NRST.
The NRST pin has no effect on the on-chip Embedded ICE
logic.
Watchdog Reset
The internally generated watchdog reset has the same
effect as the NRST pin, except that the pins BMS and NTRI
are not sampled. Boot mode and Tri-state Mode are not
updated. The NRST pin has priority if both types of reset
coincide.
Emulation Functions
Tri-state Mode
The AT91M42800 provides a Tri-state Mode, which is used
for debug purposes in order to connect an emulator probe
to an application board. In Tri-state Mode the AT91M42800
continues to function, but all the output pin drivers are tri-
stated.
To enter Tri-state Mode, the pin NTRI must be held low
during the last 10 clock cycles before the rising edge of
NRST. For normal operation, the pin NTRI must be held
high during reset, by a resistor of up to 400K Ohm. NTRI
must be driven to a valid logic value during reset.
NTRI is multiplexed with Parallel I/O PA9 and USART 1
serial data transmit line TXD1.
Standard RS232 drivers generally contain internal 400K
Ohm pull-up resistors. If TXD1 is connected to one of these
drivers this pull-up will ensure normal operation, without the
need for an additional external resistor.
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