AT91M42800-33CI Atmel, AT91M42800-33CI Datasheet - Page 8

• Manufacturer Part Number: AT91M42800-33CI
• Description: IC ARM7 MCU 144 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M42800-33CI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: WDT
• Number Of I /o: 54
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• For Use With: AT91EB42 - KIT EVAL FOR ARM AT91M42800A
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: AT91M4280033CI

Architectural Overview
T h e A T 9 1 M 4 2 8 0 0 M i c r o c o n t r o l l e r i n t e g r a t e s a n
ARM7TDMI with its embedded ICE interface, memories
and peripherals. Its architecture consists of two main
buses, the Advanced System Bus (ASB) and the Advanced
Peripheral Bus (APB). Designed for maximum performance
and controlled by the memory controller, the ASB inter-
faces the ARM7TDMI processor with the on-chip 32-bit
memories, the External Bus Interface (EBI) and the
AMBA
designed for accesses to on-chip peripherals and opti-
mized for low power consumption.
The AT91M42800 Microcontroller implements the ICE port
of the ARM7TDMI processor on dedicated pins, offering a
complete, low-cost and easy-to-use debug solution for tar-
get debugging.
Memories
The AT91M42800 Microcontroller embeds up to 8K bytes
of internal SRAM. The internal memory is directly con-
nected to the 32-bit data bus and is single-cycle accessible.
This provides maximum performance of 30 MIPS at 33
MHz by using the ARM instruction set of the processor.
The on-chip memory significantly reduces the system
power consumption and improves its performance over
external memory solutions.
The AT91M42800 Microcontroller features an External Bus
Interface (EBI), which enables connection of external mem-
ories and application-specific peripherals. The EBI
supports 8- or 16-bit devices and can use two 8-bit devices
to emulate a single 16-bit device. The EBI implements the
early read protocol, enabling faster memory accesses than
standard memory interfaces.
Peripherals
The AT91M42800 Microcontroller integrates several
peripherals, which are classified as system or user periph-
erals. All on-chip peripherals are 32-bit accessible by the
AMBA Bridge, and can be programmed with a minimum
number of instructions. The peripheral register set is com-
p o s e d
enable/disable/status registers.
An on-chip Peripheral Data Controller (PDC) transfers data
between the on-chip USARTs/SPIs and the on- and off-
chip memories without processor intervention. Most impor-
tantly, the PDC removes the processor interrupt handling
overhead and significantly reduces the number of clock
cycles required for a data transfer. It can transfer up to 64K
continuous bytes without reprogramming the start address.
As a result, the performance of the microcontroller is
increased and the power consumption reduced.
8
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Bridge. The AMBA Bridge drives the APB, which is
o f
c o n t r o l ,
AT91M42800
m o d e ,
d a t a ,
s t a t u s
a n d
System Peripherals
The External Bus Interface (EBI) controls the external
memory and peripheral devices via an 8- or 16-bit data bus
and is programmed through the APB. Each chip select line
has its own programming register.
The Power Management Controller (PMC) optimizes power
consumption of the product by controlling the clocking ele-
ments such as the oscillators and the PLL, system and
user peripheral clocks.
The Advanced Interrupt Controller (AIC) controls the inter-
nal sources from the internal peripherals and the five
external interrupt lines (including the FIQ) to provide an
interrupt and/or fast interrupt request to the ARM7TDMI. It
integrates an 8-level priority controller, and, using the Auto-
vectoring feature, reduces the interrupt latency time.
The Parallel Input/Output Controllers (PIOA, PIOB) con-
trols up to 54 I/O lines. It enables the user to select specific
pins for on-chip peripheral input/output functions, and gen-
eral-purpose input/output signal pins. The PIO controllers
can be programmed to detect an interrupt on a signal
change from each line.
There are three embedded system timers. The Real-time
Timer (RTT) counts elapsed seconds and can generate
periodic or programmed interrupts. The Period Interval
Timer (PIT) can be used as a user-programmable time-
base, and can generate periodic ticks. The Watchdog (WD)
can be used to prevent system lock-up if the software
becomes trapped in a deadlock.
The Special Function (SF) module integrates the Chip ID
and the Reset Status registers.
User Peripherals
Two USARTs, independently configurable, enable commu-
n i c a t i o n a t a h i g h b a u d r a t e i n s y n c h r o n o u s o r
asynchronous mode. The format includes start, stop and
parity bits and up to 9 data bits. Each USART also features
a Time-out and a Time-guard register, facilitating the use of
the two dedicated Peripheral Data Controller (PDC)
channels.
The two 3-channel, 16-bit Timer/Counters (TC) are highly-
programmable and support capture or waveform modes.
Each TC channel can be programmed to measure or gen-
erate different kinds of waves, and can detect and control
two input/output signals. Each TC also has three external
clock signals.
Two independently configurable SPIs provide communica-
tion with external devices in master or slave mode. Each
has four external chip selects which can be connected to
up to 15 devices. The data length is programmable, from 8-
to 16-bit.