ATMEGA161L-4AI Atmel, ATMEGA161L-4AI Datasheet - Page 30

• Manufacturer Part Number: ATMEGA161L-4AI
• Description: IC AVR MCU 16K LV 4MZ IND 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA161L-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: ATMEGA161L4AI

Interrupt Response Time
General Interrupt Mask
Register – GIMSK
30
ATmega161(L)
Note that the Status Register is not automatically stored when entering an interrupt rou-
tine or restored when returning from an interrupt routine. This must be handled by
software.
The interrupt execution response for all the enabled AVR interrupts is four clock cycles
minimum. After four clock cycles, the Program Vector address for the actual interrupt
handling routine is executed. During this four-clock-cycle period, the Program Counter
(13 bits) is pushed onto the Stack. The Vector is normally a jump to the interrupt routine,
and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-
cycle instruction, this instruction is completed before the interrupt is served. If an inter-
rupt occurs when the MCU is in Sleep mode, the interrupt execution response time is
increased by four clock cycles.
A return from an interrupt handling routine takes four clock cycles. During these four
clock cycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack
Pointer is incremented by 2, and the I-Flag in SREG is set. When AVR exits from an
interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
• Bit 7
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) in the MCU general Control Register (MCUCR) define whether the external
interrupt is activated on rising and/or falling edge of the INT1 pin or is level-sensed.
Activity on the pin will cause an interrupt request even if INT1 is configured as an output.
The corresponding interrupt of External Interrupt Request 1 is executed from Program
memory address $004. See also “External Interrupts”.
• Bit 6
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU general Control Register (MCUCR) define whether the external
interrupt is activated on rising and/or falling edge of the INT0 pin or is level-sensed.
Activity on the pin will cause an interrupt request even if INT0 is configured as an output.
The corresponding interrupt of External Interrupt Request 0 is executed from Program
memory address $002. See also “External Interrupts.”
• Bit 5 – INT2: External Interrupt Request 2 Enable
When the INT2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is activated. The Interrupt Sense Control2 bit (ISC02 in the
Extended MCU Control Register [EMCUCR]) defines whether the external interrupt is
activated on rising or falling edge of the INT2 pin. Activity on the pin will cause an inter-
rupt request even if INT2 is configured as an output. The corresponding interrupt of
External Interrupt Request 2 is executed from Program memory address $006. See also
“External Interrupts.”
Bit
$3B ($5B)
Read/Write
Initial Value
–
–
INT1: External Interrupt Request 1 Enable
INT0: External Interrupt Request 0 Enable
INT1
R/W
7
0
INT0
R/W
6
0
INT2
R
5
0
R
4
–
0
R
3
–
0
R
2
–
0
R
1
–
0
1228D–AVR–02/07
R
0
–
0
GIMSK